參數(shù)資料
型號(hào)： SAA6750
廠商： NXP Semiconductors N.V.
英文描述： Encoder for MPEG2 image recording EMPIRE
中文描述： 為MPEG2編碼器帝國(guó)的形象記錄
文件頁(yè)數(shù)： 40/60頁(yè)
文件大?。?/td> 217K
代理商： SAA6750
2000 May 03
40
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
Table 23
Description of engine bits
The engine control bits are used to set the SAA6750H in a
specific operating mode. After reset mode the init mode
will be activated automatically. For information about the
operating modes of the SAA6750H refer to Table 1.
7.9.5
I
2
C-
BUS INITIALIZATION
After power-on and the related RESETN pulse the
SAA6750H has to be initialized via the I
2
C-bus.
The internal RAMs must be loaded and the control bits
must be set.
The internal memories reachable via subaddresses 00H,
01H, 02H and 03H should be loaded first. Use the data
files that belong to a specific ASIP software version. The
control register should be written at last. Activate bit E_ST
only if all other settings have the desired state.
There has to be a 0.5 ms delay between the end of the
external reset RESETN and the start of the I
2
C-bus
initialization.
The registers and memories of the SAA6750H should be
initialized in following order:
1.
Subaddress 00H: MBP quantization matrix
2.
Subaddress 01H: ASIP microcode
3.
Subaddress 02H: ASIP microcode ROM table
4.
Subaddress 03H: ASIP microcode constant
5.
Subaddress 05H: ASIP serial input
6.
Subaddress 06H: Control register (see Table 24).
The following example shows a control register setting for
PAL input signal, SAV/EAV sync and external output port
address decoding for inter and intra mode. It should be
noted that the settings for the INTRA bit and the FIFO time
slot values are depending on a specific ASIP software
version. Use in any case those settings given in the ASIP
software specification.
E_ST
E_SP
SELECTED OPERATING MODE
0
0
1
1
0
1
0
1
init mode
soft reset mode
operating mode
internal use only
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