參數(shù)資料
型號(hào): SM320F28335GHHAEP
廠商: Texas Instruments
文件頁數(shù): 106/167頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲(chǔ)器容量: 512KB(256K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
SPRS581D – JUNE 2009 – REVISED MAY 2012
3.3
Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible
peripheral bus. See Table 3-8.
Table 3-5. Peripheral Frame 0 Registers(1)
NAME
ADDRESS RANGE
SIZE (×16)
ACCESS TYPE(2)
Device Emulation Registers
0x00 0880 - 0x00 09FF
384
EALLOW protected
FLASH Registers(3)
0x00 0A80 - 0x00 0ADF
96
EALLOW protected
Code Security Module Registers
0x00 0AE0 - 0x00 0AEF
16
EALLOW protected
ADC registers (dual-mapped)
0x00 0B00 - 0x00 0B0F
16
Not EALLOW protected
0 wait (DMA), 1 wait (CPU), read only
XINTF Registers
0x00 0B20 - 0x00 0B3F
32
Not EALLOW protected
CPU–TIMER0/1/2 Registers
0x00 0C00 - 0x00 0C3F
64
Not EALLOW protected
PIE Registers
0x00 0CE0 - 0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00 - 0x00 0DFF
256
EALLOW protected
DMA Registers
0x00 1000 - 0x00 11FF
512
EALLOW protected
(1)
Registers in Frame 0 support 16-bit and 32-bit accesses.
(2)
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3)
The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-6. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
SIZE (×16)
ECAN-A Registers
0x00 6000 - 0x00 61FF
512
ECAN-B Registers
0x00 6200 - 0x00 63FF
512
EPWM1 + HRPWM1 registers
0x00 6800 - 0x00 683F
64
EPWM2 + HRPWM2 registers
0x00 6840 - 0x00 687F
64
EPWM3 + HRPWM3 registers
0x00 6880 - 0x00 68BF
64
EPWM4 + HRPWM4 registers
0x00 68C0 - 0x00 68FF
64
EPWM5 + HRPWM5 registers
0x00 6900 - 0x00 693F
64
EPWM6 + HRPWM6 registers
0x00 6940 - 0x00 697F
64
ECAP1 registers
0x00 6A00 - 0x00 6A1F
32
ECAP2 registers
0x00 6A20 - 0x00 6A3F
32
ECAP3 registers
0x00 6A40 - 0x00 6A5F
32
ECAP4 registers
0x00 6A60 - 0x00 6A7F
32
ECAP5 registers
0x00 6A80 - 0x00 6A9F
32
ECAP6 registers
0x00 6AA0 - 0x00 6ABF
32
EQEP1 registers
0x00 6B00 - 0x00 6B3F
64
EQEP2 registers
0x00 6B40 - 0x00 6B7F
64
GPIO registers
0x00 6F80 - 0x00 6FFF
128
Copyright 2009–2012, Texas Instruments Incorporated
Functional Overview
43
Product Folder Link(s): SM320F28335-EP
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