參數(shù)資料
型號： SM320F28335GHHAEP
廠商： Texas Instruments
文件頁數(shù)： 110/167頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝： 189
系列： TMS320F28x3x Delfino™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 150MHz
連通性： CAN，EBI/EMI，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 88
程序存儲(chǔ)器容量： 512KB（256K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 34K x 16
電壓 - 電源 (Vcc/Vdd)： 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 179-LFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 718 (CN2011-ZH PDF)
其它名稱： 296-25243
INT12
MUX
INT11
INT2
INT1
CPU
(Enable)
(Flag)
INTx
INTx.8
PIEIERx(8:1)
PIEIFRx(8:1)
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals or
External
Interrupts
(Enable)
(Flag)
IER(12:1)
IFR(12:1)
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
SPRS581D – JUNE 2009 – REVISED MAY 2012
Figure 3-5. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts(1)
PIE INTERRUPTS
CPU INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
TINT0
ADCINT
SEQ2INT
SEQ1INT
INT1
XINT2
XINT1
Reserved
(LPM/WD)
(TIMER 0)
(ADC)
EPWM6_TZINT
EPWM5_TZINT
EPWM4_TZINT
EPWM3_TZINT
EPWM2_TZINT
EPWM1_TZINT
INT2
Reserved
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
EPWM6_INT
EPWM5_INT
EPWM4_INT
EPWM3_INT
EPWM2_INT
EPWM1_INT
INT3
Reserved
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
ECAP6_INT
ECAP5_INT
ECAP4_INT
ECAP3_INT
ECAP2_INT
ECAP1_INT
INT4
Reserved
(ECAP6)
(ECAP5)
(eCAP4)
(eCAP3)
(eCAP2)
(eCAP1)
EQEP2_INT
EQEP1_INT
INT5
Reserved
(eQEP2)
(eQEP1)
MXINTA
MRINTA
MXINTB
MRINTB
SPITXINTA
SPIRXINTA
INT6
Reserved
(McBSP-A)
(McBSP-B)
(SPI-A)
DINTCH6
DINTCH5
DINTCH4
DINTCH3
DINTCH2
DINTCH1
INT7
Reserved
(DMA)
SCITXINTC
SCIRXINTC
I2CINT2A
I2CINT1A
INT8
Reserved
(SCI-C)
(I2C-A)
ECAN1_INTB
ECAN0_INTB
ECAN1_INTA
ECAN0_INTA
SCITXINTB
SCIRXINTB
SCITXINTA
SCIRXINTA
INT9
(CAN-B)
(CAN-A)
(SCI-B)
(SCI-A)
INT10
Reserved
INT11
Reserved
LUF
LVF
INT12
Reserved
XINT7
XINT6
XINT5
XINT4
XINT3
(FPU)
(1)
Out of the 96 possible interrupts, 58 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
Copyright 2009–2012, Texas Instruments Incorporated
Functional Overview
47
Product Folder Link(s): SM320F28335-EP
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