參數(shù)資料
型號(hào)： SM320F28335GHHAEP
廠商： Texas Instruments
文件頁數(shù)： 40/167頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝： 189
系列： TMS320F28x3x Delfino™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 150MHz
連通性： CAN，EBI/EMI，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 88
程序存儲(chǔ)器容量： 512KB（256K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 34K x 16
電壓 - 電源 (Vcc/Vdd)： 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 179-LFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 718 (CN2011-ZH PDF)
其它名稱： 296-25243
SPRS581D – JUNE 2009 – REVISED MAY 2012
Examples:
XZCSL
Zone chip-select active low
XRNWL
XR/W active low
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if
the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK
cycles is odd, then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XRD active low
XWEL
XWE1 or XWE0 active low
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the
total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If
the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment
will be with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XRD inactive high
XWEH
XWE1 or XWE0 inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total
number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XRNWH
XR/W inactive high
6.14.5 External Interface Read Timing
Table 6-37. External Interface Read Timing Requirements
MIN
MAX
UNIT
ta(A)
Access time, read data from address valid
(LR + AR) –16 (1)
ns
ta(XRD)
Access time, read data valid from XRD active low
AR –14 (1)
ns
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
14
ns
th(XD)XRD
Hold time, read data valid after XRD inactive high
0
ns
(1)
LR = Lead period, read access. AR = Active period, read access. See Table 6-35.
Table 6-38. External Interface Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
1
ns
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
–1
0.5
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
1.5
ns
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
0.5
ns
td(XCOHL-XRDH
Delay time, XCLKOUT high/low to XRD inactive high
–1.5
0.5
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
ns
th(XA)XRD
Hold time, address valid after XRD inactive high
(1)
ns
(1)
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
134
Electrical Specifications
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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