參數(shù)資料
型號(hào): SM320F28335GHHAEP
廠商: Texas Instruments
文件頁數(shù): 34/167頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲(chǔ)器容量: 512KB(256K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE(A)
SPRS581D – JUNE 2009 – REVISED MAY 2012
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-34. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3) (4)
NO.
MIN
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
8tc(LCO)
ns
13
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC) S
ns
14
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC) S
ns
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
17
tsu(SOMI-SPCH)S
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
0.125tc(SPC)S
ns
tsu(SOMI-SPCL)S
Setup time, SPISOMI before SPICLK low (clock polarity = 1
0.125tc(SPC)S
ns
18
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
0.75tc(SPC)S
ns
(clock polarity = 0)
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
0.75tc(SPC) S
ns
(clock polarity = 1)
21
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
35
ns
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
35
ns
22
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
0.5tc(SPC)S-10
ns
(clock polarity = 0)
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
0.5tc(SPC)S-10
ns
(clock polarity = 1)
(1)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2)
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Copyright 2009–2012, Texas Instruments Incorporated
Electrical Specifications
129
Product Folder Link(s): SM320F28335-EP
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