參數(shù)資料
型號： SM320F28335GHHAEP
廠商： Texas Instruments
文件頁數(shù)： 36/167頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓模塊： ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標準包裝： 189
系列： TMS320F28x3x Delfino™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 150MHz
連通性： CAN，EBI/EMI，I²C，McBSP，SCI，SPI，UART/USART
外圍設備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 88
程序存儲器容量： 512KB（256K x 16）
程序存儲器類型： 閃存
RAM 容量： 34K x 16
電壓 - 電源 (Vcc/Vdd)： 1.805 V ~ 1.995 V
數(shù)據(jù)轉換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 179-LFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 718 (CN2011-ZH PDF)
其它名稱： 296-25243
Data Valid
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21
12
18
17
14
13
SPISTE(A)
SPRS581D – JUNE 2009 – REVISED MAY 2012
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-22. SPI Slave Mode External Timing (Clock Phase = 1)
6.14 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-35 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-35. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
DURATION (ns)(1) (2)
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
XRDLEAD × tc(XTIM)
(XRDLEAD × 2) × tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1) × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
TR
Trail period, read access
XRDTRAIL × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
LW
Lead period, write access
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1) × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
TW
Trail period, write access
XWRTRAIL × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1)
tc(XTIM) Cycle time, XTIMCLK
(2)
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
6.14.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
130
Electrical Specifications
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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