(Toggling 0 VDDIO) XCLKIN X2 NC X1 External Clock Signal <" />
參數(shù)資料
型號: SM320F28335GHHAEP
廠商: Texas Instruments
文件頁數(shù): 116/167頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲器容量: 512KB(256K x 16)
程序存儲器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
External Clock Signal
(Toggling 0 VDDIO)
XCLKIN
X2
NC
X1
External Clock Signal
(Toggling 0 VDD)
XCLKIN
X2
NC
X1
CL1
X2
X1
Crystal
CL2
XCLKIN
SPRS581D – JUNE 2009 – REVISED MAY 2012
Figure 3-8. Using a 3.3-V External Oscillator
Figure 3-9. Using a 1.9-V External Oscillator
Figure 3-10. Using the Internal Oscillator
3.6.1.1
External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 25 to 40
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSC chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
3.6.1.2
PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
131072 OSCCLK cycles. The input clock and PLLCR[DIV] bits should be chosen in such a way that the
output frequency of the PLL (VCOCLK) does not exceed 300 MHz.
52
Functional Overview
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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