td(HL-Hiz)
參數(shù)資料
型號: SM320F28335GHHAEP
廠商: Texas Instruments
文件頁數(shù): 51/167頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲(chǔ)器容量: 512KB(256K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
XCLKOUT
(/1 Mode)
XHOLD
XZCS0, XZCS6, XZCS7
XD[31:0], XD[15:0]
Valid
XHOLDA
td(HL-Hiz)
td(HH-HAH)
High-Impedance
XA[19:0]
Valid
High-Impedance
td(HH-BV)
td(HL-HAL)
(A)
(B)
XR/W
SPRS581D – JUNE 2009 – REVISED MAY 2012
A.
All pending XINTF accesses are completed.
B.
Normal XINTF operation resumes.
Figure 6-30. External Interface Hold Waveform
Table 6-48. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)(1) (2) (3)
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all address, data, and
4tc(XTIM) + tc(XCO) + 30 ns
ns
control
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
4tc(XTIM + 2tc(XCO) + 30 ns
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
4tc(XTIM) + 30 ns
ns
td(HH-BV)
Delay time, XHOLD high to bus valid
6tc(XTIM) + 30 ns
ns
(1)
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2)
The state of XHOLD is latched on the rising edge of XTIMCLK.
(3)
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
144
Electrical Specifications
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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