
Lead 1
Active
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XA[0:19]
td(XCOHL-XWEH)
td(XCOHL-XZCSH)
td(XCOH-XA)
WS (Async)
XZCS0, XZCS6, XZCS7
XRD
XWE0, XWE1(D)
XR/W
td(XCOH-XZCSL)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
th(XD)XWEH
th(XRDYasynchL)
DOUT
tdis(XD)XRNW
th(XRDYasynchH)XZCSH
(E)
(D)
= Don’t care. Signal can be high or low during this time.
Legend:
tsu(XRDYasynchL)XCOHL
tsu(XRDYasynchH)XCOHL
td(XWEL-XD
)
td(XCOHL-XWEL)
(A) (B)
(C)
te(XRDYasynchH)
XREADY(Asynch)
XD[31:0], XD[15:0]
SPRS581D – JUNE 2009 – REVISED MAY 2012
A.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B.
During alignment cycles, all signals transition to their inactive state.
C.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D.
XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
E.
For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
F.
Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 6-29. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
1
0
≥ 1
3
≥ 1
1 = XREADY
(Async)
(1)
N/A = “Don’t care” for this example
142
Electrical Specifications
Copyright 2009–2012, Texas Instruments Incorporated