tsu(XD)XRD Lead Active Trail DIN td(XCOH-XZCSL)
參數(shù)資料
型號(hào): SM320F28335GHHAEP
廠商: Texas Instruments
文件頁數(shù): 45/167頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲(chǔ)器容量: 512KB(256K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
tsu(XD)XRD
Lead
Active
Trail
DIN
td(XCOH-XZCSL)
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XZCSH)
td(XCOHL-XRDH)
WS (Async)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
XWE0, XWE1(D)
XR/W
XD[0:31], XD[0:15]
XREADY(Asynch)
tsu(XRDYasynchL)XCOHL
ta(XRD)
ta(A)
th(XRDYasynchL)
th(XD)XRD
th(XRDYasynchH)XZCSH
= Don’t care. Signal can be high or low during this time.
Legend:
(A) (B)
(C)
tsu(XRDYasynchH)XCOHL
(E)
(F)
te(XRDYasynchH)
SPRS581D – JUNE 2009 – REVISED MAY 2012
A.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B.
During alignment cycles, all signals will transition to their inactive state.
C.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D.
XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E.
For
each
sample,
setup
time
from
the
beginning
of
the
access
can
be
calculated
as:
E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and
so forth.
F.
Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 6-27. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
3
≥ 1
1
0
N/A(1)
1 = XREADY
(Async)
(1)
N/A = “Don’t care” for this example
Copyright 2009–2012, Texas Instruments Incorporated
Electrical Specifications
139
Product Folder Link(s): SM320F28335-EP
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