參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 105/140頁
文件大小: 1310K
代理商: SPC563M64L5COAY
Pinout and signal description
SPC563M64
Doc ID 14642 Rev 6
EVTI
Nexus
EVTI is an input that is read on the negation of RESET to
enable or disable the Nexus Debug port. After reset, the EVTI
pin is used to initiate program synchronization messages or
generate a breakpoint.
EVTO
Nexus
Output that provides timing to a development tool for a single
watchpoint or breakpoint occurrence.
MCKO
Nexus
MCKO is a free running clock output to the development tools
which is used for timing of the MDO and MSEO signals.
MDO[3:0]
Nexus
Trace message output to development tools. This pin also
indicates the status of the crystal oscillator clock following a
power-on reset, when MDO[0] is driven high until the crystal
oscillator clock achieves stability and is then negated.
MSEO[1:0]
Nexus
Output pin—Indicates the start or end of the variable length
message on the MDO pins
BOOTCFG[1]
SIU - Configuration
The BOOTCFG1 pin is sampled during the assertion of the
RSTOUT signal, and the value is used to update the RSR and
the BAM boot mode
The following values are for BOOTCFG[0:1}:
0:Boot from internal flash memory
1:FlexCAN/eSCI boot
WKPCFG
SIU - Configuration
The WKPCFG pin is applied at the assertion of the internal
reset signal (assertion of RSTOUT), and is sampled 4 clock
cycles before the negation of the RSTOUT pin.
The value is used to configure whether the eTPU and eMIOS
pins are connected to internal weak pull up or weak pull down
devices after reset. The value latched on the WKPCFG pin at
reset is stored in the Reset Status Register (RSR), and is
updated for all reset sources except the Debug Port Reset and
Software External Reset.
0:Weak pulldown applied to eTPU and eMIOS pins at reset
1:Weak pullup applied to eTPU and eMIOS pins at reset.
ETRIG[2:3]
SIU - eQADC Triggers
External signal eTRIGx triggers eQADC CFIFOx
IRQ[0:15]
SIU - External
Interrupts
The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select
Register 1 is used to select the IRQ[0:15] pins as inputs to the
IRQs.
NMI
SIU - External
Interrupts
Non-Maskable Interrupt
GPIO[n]
SIU - GPIO
Configurable general purpose I/O pins. Each GPIO input and
output is separately controlled by an 8-bit input (GPDI) or
output (GPDO) register. Additionally, each GPIO pins is
configured using a dedicated SIU_PCR register.
The GPIO pins are generally multiplexed with other I/O pin
functions.
Table 6.
Signal details (continued)
Signal
Module or function
Description
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