參數(shù)資料
型號(hào): SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 71/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
SPC563M64
Overview
Doc ID 14642 Rev 6
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register
1.3.20
Debug Features
Nexus Port Controller
The NPC (Nexus Port Controller) block provides real-time development support capabilities
for the SPC563Mxx Power Architecture-based MCU in compliance with the IEEE-ISTO
5001-2003 standard. This development support is supplied for MCUs without requiring
external address and data pins for internal visibility. The NPC block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for the SPC563Mxx. The NPC block interfaces to the host processor (e200z335),
eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003
standard. The development support provided includes program trace and run-time access to
the MCUs internal memory map and access to the Power Architecture and eTPU internal
registers during halt. The Nexus interface also supports a JTAG only mode using only the
JTAG pins. SPC563Mxx in the production LQFP144 supports a 3.3 V reduced (4-bit wide)
Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable
I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using
calibration tool calibration. In the calibration tool calibration package, the full 12-bit Auxiliary
port is available.
Note:
In the calibration tool package, the full Nexus Auxiliary port shares balls with the addresses
of the calibration bus. Therefore multiplexed address/data bus mode must be used for the
calibration bus when using full width Nexus trace in calibration tool assembly.
The following features are implemented:
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
Always available in production package
Supports both JTAG Boundary Scan and debug modes
–3.3 V interface
Supports Nexus class 1 features
Supports Nexus class 3 read/write feature
9-pin Reduced Port interface in LQFP144 production package
Alternate function as IO
5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface
Auxiliary Output port
1 MCKO (message clock out) pin
4 MDO (message data out) pins
2 MSEO (message start/end out) pins
1 EVTO (event out) pin
Auxiliary input port
1 EVTI (event in) pin
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