參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 9/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
SPC563M64
Electrical characteristics
Doc ID 14642 Rev 6
106/140
3.16.2
Nexus timing
Table 36.
Nexus debug port timing(1)
1.
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing
specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, TA
= TL to TH, and CL = 30 pF with DSC = 0b10.
#
Symbol
C
Characteristic
Min. Value Max. Value
Unit
1tMCYC
CC
D
MCKO Cycle Time
2(2),(3)
2.
Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting
(NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.
3.
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute
minimum MCKO period specification.
8tCYC
1a
tMCYC
CC
D
Absolute Minimum MCKO Cycle Time
100(4)
4.
This may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on the
actual system frequency being used.
—ns
2tMDC
CC
D
MCKO Duty Cycle
40
60
%
3tMDOV
CC
D
MCKO Low to MDO Data Valid(5)
5.
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
– 0.1
0.2
tMCYC
4tMSEOV
CC
D
MCKO Low to MSEO Data Valid(5)
0.1
0.2
tMCYC
6tEVTOV
CC
D
MCKO Low to EVTO Data Valid(5)
– 0.1
0.2
tMCYC
7tEVTIPW
CC
D
EVTI Pulse Width
4.0
tTCYC
8tEVTOPW
CC
D
EVTO Pulse Width
1
tMCYC
9tTCYC
CC
D
TCK Cycle Time
4(6),(7)
6.
Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency
being used.
7.
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
—tCYC
9a
tTCYC
CC
D
Absolute Minimum TCK Cycle Time
100(8)
8.
This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.
—ns
10
tTDC
CC
D
TCK Duty Cycle
40
60
%
11
tNTDIS
CC
D
TDI Data Setup Time
5
ns
12
tNTDIH
CC
D
TDI Data Hold Time
25
ns
13
tNTMSS
CC
D
TMS Data Setup Time
5
ns
14
tNTMSH
CC
D
TMS Data Hold Time
25
ns
15
tJOV
CC
D
TCK Low to TDO Data Valid
10
20
ns
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