參數(shù)資料
型號(hào): SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 19/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
Electrical characteristics
SPC563M64
115/140
Doc ID 14642 Rev 6
12
tHO
CC
Data Hold Time for Outputs
D
Master (MTFE = 0)
–5
–5
–5
ns
D
Slave
5.5
5.5
5.5
D
Master (MTFE = 1,
CPHA = 0)
8—4—3—
D
Master (MTFE = 1,
CPHA = 1)
–5
–5
–5
1.
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types
of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V, TA = TL to
TH, and CL = 50 pF with SRC = 0b11.
2.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation
(FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 66 MHz parts allow for a 64 MHz system clock + 2% FM, and
82 MHz parts allow for 80 MHz system clock + 2% FM.
3.
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two SPC563Mxx devices communicating over a DSPI link.
4.
The actual minimum SCK cycle time is limited by pad performance.
5.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
6.
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
7.
This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
Table 39.
DSPI timing(1),(2) (continued)
#
Symbol
C
Characteristic
40 MHz
64 MHz
80 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
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