參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 50/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
Overview
SPC563M64
Doc ID 14642 Rev 6
Two deserial serial peripheral interface modules (DSPI)
–SPI
Full duplex communication ports with interrupt and DMA request support
Support for queues in RAM
6 chip selects, expandable to 64 with external demultiplexers
Programmable frame size, baud rate, clock delay and clock phase on a per frame
basis
Modified SPI mode for interfacing to peripherals with longer setup time
requirements
LVDS option for output clock and data to allow higher speed communication
Deserial serial interface (DSI)
Pin reduction by hardware serialization and deserialization of eTPU, eMIOS
channels and GPIO
32 bits per DSPI module
Triggered transfer control and change in data transfer control (for reduced EMI)
Compatible with Microsecond Bus Version 1.0 downlink
Two enhanced serial communication interface (eSCI) modules
UART mode provides NRZ format and half or full duplex interface
eSCI bit rate up to 1 Mbps
Advanced error detection, and optional parity generation and detection
Word length programmable as 8, 9, 12 or 13 bits
Separately enabled transmitter and receiver
LIN support
DMA support
Interrupt request support
Programmable clock source: system clock or oscillator clock
Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0
Two FlexCAN
One with 32 message buffers; the second with 64 message buffers
Full implementation of the CAN protocol specification, Version 2.0B
Programmable acceptance filters
Short latency time for high priority transmit messages
Arbitration scheme according to message ID or message buffer number
Listen only mode capabilities
Programmable clock source: system clock or oscillator clock
Message buffers may be configured as mailboxes or as FIFO
Nexus port controller (NPC)
Per IEEE-ISTO 5001-2003
Real time development support for Power Architecture core and eTPU engine
through Nexus class 2/1
Read and write access (Nexus class 3 feature that is supported on this device)
Run-time access of entire memory map
Calibration
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