
SPC563M64
Electrical characteristics
Doc ID 14642 Rev 6
3.3
Thermal characteristics
2.
Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.
3.
The VFLASH supply is connected to VRC33 in the package substrate. This specification applies to calibration package
devices only.
4.
Allowed 5.3 V for 10 hours cumulative time, remaining time at 3.3 V +10%.
5.
Allowed 6.8 V for 10 hours cumulative time, remaining time at 5 V +10%.
6.
The pin named as VRC33 is internally connected to the pads VFLASH and VRC33 in the LQFP144 package. These limits
apply when the internal regulator is disabled and VRC33 power is supplied externally.
7.
All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH.
8.
AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60
hours over the complete lifetime of the device (injection current not limited for this duration).
9.
Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.
10. Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications.
11. Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
12. Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
13. Total injection current for all analog input pins must not exceed 15 mA.
14. Lifetime operation at these specification limits is not guaranteed.
15. Solder profile per CDF-AEC-Q100.
16. Moisture sensitivity per JEDEC test method A112.
Table 10.
Thermal characteristics for 100-pin LQFP(1)
1.
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Symbol
C
Parameter
Conditions
Value
Unit
RθJA
CC
D Junction-to-Ambient, Natural Convection(2)
2.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
Single layer board - 1s
47
°C/W
RθJA
CC
D Junction-to-Ambient, Natural Convectio
n(2)Four layer board - 2s2p
35
°C/W
RθJMA
CC
Single layer board
37
°C/W
RθJMA
CC
Four layer board 2s2p
29
°C/W
RθJB
CC
D Junction-to-Board(3)
3.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
20
°C/W
RθJCtop
CC
D Junction-to-Case (Top)(4)
4.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
9°C/W
ΨJT
CC
D
Junction-to-Package Top, Natural
Convection(5)
5.
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
2°C/W