參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 72/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
Overview
SPC563M64
Doc ID 14642 Rev 6
17-pin Full Port interface in calibration tool calibration package
–3.3 V interface
Auxiliary Output port
1 MCKO (message clock out) pin
4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins; 8
extra full port pins shared with calibration bus
2 MSEO (message start/end out) pins
1 EVTO (event out) pin
Auxiliary input port
1 EVTI (event in) pin
Host processor (e200) development support features
IEEE-ISTO 5001-2003 standard class 2 compliant
Program trace via branch trace messaging (BTM). Branch trace messaging
displays program flow discontinuities (direct branches, indirect branches,
exceptions, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus, static code may be traced.
Watchpoint trigger enable of program trace messaging
Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be
halted when the CPU writes a specific value to a memory location
4 data value breakpoints
CPU only
Detects ‘equal’ and ‘not equal’
Byte, half word, word (naturally aligned)
Note:
This feature is imprecise due to CPU pipelining.
Subset of Power Architecture Technology software debug facilities with OnCE
block (Nexus class 1 features)
eTPU development support features
IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU
Nexus based breakpoint configuration and single step support (JTAG feature of
the eTPU)
Run-time access to the on-chip memory map via the Nexus read/write access protocol.
This feature supports accesses for run-time internal visibility, calibration variable
acquisition, calibration constant tuning, and external rapid prototyping for powertrain
automotive development systems.
All features are independently configurable and controllable via the IEEE 1149.1 I/O
port
Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. Testing is
performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All
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相關代理商/技術參數(shù)
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