參數(shù)資料
型號(hào): SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 61/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
Overview
SPC563M64
Doc ID 14642 Rev 6
Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:
Input Period Measurement (IPM)
Input Pulse Width Measurement (IPWM)
Double Action Output Compare (set flag on both matches) (DAOC)
Modulus Counter Buffered (MCB)
Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
Three 24-bit wide counter buses
Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can
use it as a reference
Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference
Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a
reference
Shared time bases with the eTPU through the counter buses
Synchronization among internal and external time bases
1.3.13
eTPU2
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel
with the host CPU, eTPU2 processes instructions and real-time input events, performs
output waveform generation, and accesses shared data without host intervention.
Consequently, for each timer event, the host CPU setup and service times are minimized or
eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own
instruction and data RAM. High-level assembler/compiler and documentation allows
customers to develop their own functions on the eTPU2.
The eTPU2 includes these distinctive features:
32 channels, each channel is associated with one input and one output signal
Enhanced input digital filters on the input pins for improved noise immunity.
Identical, orthogonal channels: each channel can perform any time function. Each
time function can be assigned to more than one channel at a given time, so each
signal can have any functionality.
Each channel has an event mechanism which supports single and double action
functionality in various combinations. It includes two 24-bit capture registers, two
24-bit match registers, 24-bit greater-equal and equal-only comparators
Input and output signal states visible from the host
2 independent 24-bit time bases for channel synchronization:
First time base clocked by system clock with programmable prescale division from
2 to 512 (in steps of 2), or by output of second time base prescaler
Second time base counter can work as a continuous angle counter, enabling
angle based applications to match angle instead of time
Both time bases can be exported to the eMIOS timer module
Both time bases visible from the host
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