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參數(shù)資料
| 型號： | SPC563M64L5COAY |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, LEAD FREE, LQFP-144 |
| 文件頁數(shù)： | 51/140頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | SPC563M64L5COAY |
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SPC563M64
Overview
Doc ID 14642 Rev 6
–
Support for data value breakpoints / watchpoints
Run-time access of entire memory map
Calibration:
Table constants calibrated using MMU and internal and external RAM
Scalar constants calibrated using cache line locking
–
Configured via the IEEE 1149.1 (JTAG) port
●
IEEE 1149.1 JTAG controller (JTAGC)
–
IEEE 1149.1-2001 Test Access Port (TAP) interface
–
5-bit instruction register that supports IEEE 1149.1-2001 defined instructions
–
5-bit instruction register that supports additional public instructions
–
Three test data registers: a bypass register, a boundary scan register, and a
device identification register
–
Censorship disable register. By writing the 64-bit serial boot password to this
register, Censorship may be disabled until the next reset
–
TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
●
On-chip Voltage Regulator for single 5 V supply operation
–
On-chip regulator 5 V to 3.3 V for internal supplies
–
On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core
logic
●
Low-power modes
–
SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz),
with modules (including the PLL) selectively disabled in software
–
STOP Mode. System clock stopped to all modules including the CPU. Wake-up
timer used to restart the system clock after a predetermined time
1.3
SPC563Mxx feature details
1.3.1
e200z335 core
The e200z335 processor utilizes a four stage pipeline for instruction execution. The
Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address
Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4)
stages operate in an overlapped fashion, allowing single clock instruction execution for most
instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-
bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation
Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32
×32 Hardware Multiplier array, result
feed-forward hardware, and support hardware for division.
Most arithmetic and logical operations are executed in a single cycle with the exception of
the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The
Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to
minimize delays during change of flow operations. Sequential prefetching is performed to
ensure a supply of instructions into the execution pipeline. Branch target prefetching is
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SPC563M64L7COAR | 功能描述:32位微控制器 - MCU 32-BIT Embedded MCU 80 MHz, 1.5 Mbyte RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| SPC563M64L7COAY | 制造商:STMicroelectronics 功能描述:JDP MICRO - Bulk |
| SPC563M64L7-ENG | 制造商:STMicroelectronics 功能描述:ENG SAMPLES - Bulk |
| SPC563MADPT144S | 功能描述:32位微控制器 - MCU Socketed Mini Mod SPC563M QFP144 RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| SPC563MADPT176S | 功能描述:32位微控制器 - MCU Socketed Mini Mod SPC563M QFP176 RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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