參數(shù)資料
型號： T7121-PL2
英文描述： T7121 HDLC Interface for ISDN
中文描述： T7121的HDLC接口用于ISDN
文件頁數(shù)： 28/68頁
文件大?。?/td> 685K
代理商： T7121-PL2
28
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
3-State Mode
The HIFI-64 can be placed in a high-impedance mode for test purposes. In this configuration, all output pins are
placed in a 3-state condition. This can be accomplished in two different ways:
1. Asserting the RESET pin 3-states all outputs, clears both the transmit and receive FIFOs, and resets all internal
registers to their default values. A full chip reset occurs with or without a clock input.
2. Setting the 3STATE bit (R6—B6) to 1 3-states all outputs without affecting the states of internal registers and
FIFOs. This state lasts until both
CS
and
RD
are held low; that is, the first read of the HIFI-64 resets the 3STATE
bit regardless of the register address. Registers can be written while the 3STATE bit is enabled.
Setting the receiver reset (RRES) and the transmitter reset (TRES) bits in the operation control register
(R6—B4,B5) to 1 simultaneously causes a FIFO and register reset to reset values (outputs are not 3-stated).
Other
The HIFI-64 can be instructed to transmit a bad CRC for test purposes by programming the TBCRC bit in register
14 (R14—B7) to 1. Bad CRCs are transmitted until the TBCRC bit is cleared. The TEST bit in AR11 is used for
manufacture testing and should always be programmed low (0) by the host microprocessor.
Powerdown Mode
The HIFI-64 can be placed in a low-power mode when not in use by setting the PDWN bit in register 6 (R6—B7) to
1. This has the effect of stopping data clock input signals (CLKR and CLKX) from propagating internally and results
in very low power dissipation. Reads and writes to the HIFI-64 can continue normally. The low-power mode is
exited by clearing the PDWN bit (R6—B7) to 0.
Registers
The HIFI-64 contains 19 registers (R0—R15 and AR11—AR13). Registers 11, 12, and 13 have alternate meanings
depending on the value of the ALT bit in the Chip Configuration Register (R0—B4). The alternate registers are
accessed by setting the ALT bit (R0—B4) to 1. All subsequent addressing of registers 11 through 13 then refers to
the alternate registers (AR11—AR13). Returning to the foreground register set is accomplished by clearing the ALT
bit (R0—B4) to 0. The primary function of the alternate registers is for transparent-mode operation.
A summary of the HIFI-64 register set is given in Table 6.
相關(guān)PDF資料
PDF描述
T7121 HDLC Interface for ISDN (HIFI-64)(應(yīng)用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口)
T7502 T7502 Dual PCM Codec with Filters
T7503 T7503 Dual PCM Codec with Filters
T7504 T7504 and T75504 Quad PCM Codecs with Filters
T7507 T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T7122 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE
T7-122A1 功能描述:撥動(dòng)開關(guān) ON NONE OFF 1 Pole Low-Level Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-122B1 功能描述:撥動(dòng)開關(guān) ON NONE ON 1 Pole Low-Level Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-122D1 制造商:OTTO 功能描述:Toggle Switches (ON) NONE ON 1 Pole Low-Level Bat Handle 制造商:OTTO Engineering Inc 功能描述:Switch Toggle (ON) None ON SPDT Bat Toggle Screw 16A 115VAC 28VDC Panel Mount with Threads
T7-122E1 制造商:OTTO 功能描述:Toggle Switches (ON) OFF (ON) 1 Pole Low-Level Bat Handle 制造商:OTTO Engineering Inc 功能描述:Switch Toggle (ON) OFF (ON) SPDT Bat Toggle Screw 16A 115VAC 28VDC Panel Mount with Threads
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*