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參數(shù)資料
| 型號： | T7121-PL2 |
| 英文描述： | T7121 HDLC Interface for ISDN |
| 中文描述： | T7121的HDLC接口用于ISDN |
| 文件頁數(shù)： | 39/68頁 |
| 文件大?。?/td> | 685K |
| 代理商： | T7121-PL2 |
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Lucent Technologies Inc.
39
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Table 18. Register R11—Receiver Time-Slot Offset Control Register
R11—B7
DRI
(0)
R11—B6
RLBIT
(1)
R11—B5
RTSOF5
(0)
R11—B4
RTSOF4
(0)
R11—B3
RTSOF3
(0)
R11—B2
RTSOF2
(0)
R11—B1
RTSOF1
(0)
R11—B0
RTSOF0
(0)
Register
R11
Bit
Symbol
Name/Function
B(0—5)
RTSOF0—RTSOF5
Receiver Time-Slot Offset.
The value of these 6 bits, coded in
binary with bit 0 being the LSB, specifies the number of time slots
to delay between the beginning of the first locatable TDM highway
time slot and the beginning of a new virtual TDM frame (i.e., the
time slot defined by the user as time slot 0.) See Figure 5 for an
example of using the RTSOF bits.
RLBIT
Receive Least Significant Bit First.
This bit is used to control
whether the least significant or most significant data bit is
received first. The least significant data bit in the receive FIFO is
defined as that bit which is read on AD0 when the FIFO is read.
When RLBIT is 0, the most significant bit of data is received first,
and when RLBIT is set to 1, the least significant bit of data is
received first.
R11
B6
RLBIT has no meaning when not in the TDM highway mode (i.e.,
HWYEN, R0—B7 = 0). In non-TDM highway mode, data is
always received least significant bit first.
Receive Data Inverted.
If this bit is set to 1, the serial data input
to the DRA (or DRB) pin is inverted before data is passed to the
HDLC receiver (or FIFO in the transparent mode).
R11
B7
DRI
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