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參數(shù)資料
| 型號： | T7121-PL2 |
| 英文描述： | T7121 HDLC Interface for ISDN |
| 中文描述： | T7121的HDLC接口用于ISDN |
| 文件頁數(shù)： | 65/68頁 |
| 文件大?。?/td> | 685K |
| 代理商： | T7121-PL2 |
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Lucent Technologies Inc.
65
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Appendix
(continued)
Q14
: Does TLBIT (R10, b6) reorder the CRC bits
A14
: Yes, the TLBIT operates on every byte, including
the CRC.
Q15
: When transmitting multiple frames, is it neces-
sary to wait until one frame is transmitted before
loading the next frame
A15
: No. The operation would be as follows: load the
first frame, set TFC (R1, b7), then load the next
frame, and set TFC again without any wait time,
making sure not to overflow the transmit buffer.
Q16
: Is it possible to detect the presence of a received
open flag by using the MATCH capability and
then changing to the HDLC mode
A16
: If there is a long enough string of open flags to
permit the transmitter and receiver to be dis-
abled, individually reset them, shift into the HDLC
mode, and enable the transmitter and receiver;
otherwise, the HDLC processor will not see the
open flag, and the frame will be lost. Also, the
transmitter will not gracefully switch states on
byte boundaries, and this could be a problem at
the far-end receiver.
Another approach for detecting the open flag in
the transparent mode is to set the receiver fill
level to 1. As soon as the flag is received, an
interrupt can be issued.
Q17
: In the discussion of ALOCT (AR11, b4), what is
meant by “octet boundary”
A17
: If HWYEN (R0, b7) = 1, octet boundaries are
aligned with time-slot boundaries. If HWYEN = 0,
they are relative to (i.e., aligned with or offset by
eight data clock multiples) the first receive clock
edge after the receiver has been enabled (ENR,
R6, b2 = 1). When ALOCT is a one, checks for
match bytes are only made to data bytes aligned
with octets having these boundaries.
Q18
: When setting 2, 4, 8 (etc.) time slots on the CHI,
is it correct to assume that the T7121 can operate
the bit masking function
A18
: The bit masking option is only available when the
TDM highway mode is used. Masking a received
bit means that the bit is thrown away and is not
passed to the receiver. When the eighth bit is
passed to the receiver, it places those 8 bits in
the receive FIFO. See Table 30 in the following
example.
For example:
Receiver Bit Mask 01111111 = mask most significant
bit (MSB), receive least significant bit (LSB) first.
Masking a transmit bit means that during the transmis-
sion time of that bit, the transmitter is 3-stated. The bit
stream from the transmitter is not shifted forward; i.e.,
the data bits are placed in the transmit FIFO, and are
then transmitted bit-by-bit by using each allocated bit
time, and no bits are lost.
For example:
Transmitter Bit Mask 01111111 = mask most significant
bit (MSB), receive least significant bit (LSB) first.
Note
: The effective data rate is 56 Kbytes/s.
Q19
: An unexpected TE occurs in R15 at the start of
transmission. Why
A19
: The unexpected TE is most likely the initial trans-
mitter empty flag generated after reset. After
powerup or reset, the TE bit will be set (because
the FIFO is initially empty).
Table 30. Bit Receiving and Masking
Received Bits
Mask Applied
Bits Passed
to Receiver
11001100
11111110
1100110-
11000001
11111110
1100000-
11000011
11111110
1100001-
Receive FIFO Contents
MSB
LSB
Description
First Word Placed in
FIFO
Second Word Placed in
FIFO
1 0 1 1 0 0 1 1
1 1 0 0 0 0 0 1
. . . 1 0 0 0 0
Table 31. Bit Transmitting and Masking
Mask Applied
Transmit Pin
Output
11111110
0101010Z
11111110
1001100Z
11111110
11 . . .
Transmit FIFO Contents
MSB
LSB
Description
Transmit FIFO Contents
First Byte to Transmit
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
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