參數(shù)資料
型號: T7121-PL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁數(shù): 53/68頁
文件大?。?/td> 685K
代理商: T7121-PL2
Lucent Technologies Inc.
53
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Timing Characteristics
(continued)
Separate Address and Data
Address on A3—A0, data on AD7—AD0.
* It is recommended that ALE be tied high when separate address and data bits are used. If ALE is pulled low, the T7121 enters multiplexed
address and data mode. ALE must then be held high for five master clock cycles, to switch back to separate address and data mode. ALE
must remain high during read and write operations.
This is the time needed to update the receive FIFO status RQS (R4 B[6—0]).
Table 27. Separate Address and Data
Symbol on
Diagram
A
B
C
D
E
F
G
H
I
J
Name
Parameter
Min
Max
Unit
tALHCSL
tRWHALL
tAVRDL
tWRHAI
tRDHAI
tDVWRH
tWRHDI
tCSLRWL
tWRLWRH
tRDLDV
ALE High to
CS
Low*
RD
or
WR
High to ALE Low*
Address Valid to
RD
or
WR
Low*
Address Hold After
WR
High
Address Hold After
RD
High
Data Valid to
WR
High
Data Hold After
WR
High
CS
Low to
RD
or
WR
Low
WR
Pulse Width
RD
Low to Data Valid (register 2 or 4)
RD
Low to Data Valid (all others)
RD
High to Data 3-state
RD
Pulse Width
WR
High to
CS
High
RD
High to
CS
High
Master Clock Period
WR
High to
WR
Low
(minimum time between writes)
RD
High to
RD
Low
(minimum time between reads);
Read R3 to Read R4
5 tMCLMCL
1/2 tMCLMCL
35
20
0
35
10
0
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tMCLMCL + 40
tMCLMCL
25
<1/2 tDCLDCL
K
L
M
N
O
P
tRDHDI
tRDLRDH
tWRHCSH
tRDHCSH
tMCLMCL
tWRHWRL
tMCLMCL 40
0
10
83.3
2 tMCLMCL
Q
tRDHRDL
4 tMCLMCL
ns
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