參數(shù)資料
型號(hào): T7121-PL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁(yè)數(shù): 37/68頁(yè)
文件大?。?/td> 685K
代理商: T7121-PL2
Lucent Technologies Inc.
37
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Table 16. Register R9—Bit Offset Control Register
R9—B7
TBOF2
(0)
R9—B6
TBOF1
(0)
R9—B5
TBOF0
(0)
R9—B4
CLKXI
(0)
R9—B3
RBOF2
(0)
R9—B2
RBOF1
(0)
R9—B1
RBOF0
(0)
R9—B0
CLKRI
(1)
Register
R9
Bit
B0
Symbol
CLKRI
Name/Function
Receive Clock Invert.
When this bit is cleared to 0, data is received
(latched) on the falling edge of CLKR (or CLKX if R5 B6 is set to 1). If
this bit is set to 1, data is received (latched) on the rising edge of
CLKR (or CLKX).
RBOF0—RBOF2
Receiver Bit Offset.
These 3 bits provide a fixed offset relative to the
position of the first receivable bit after the frame-sync signal. The posi-
tion of the first receivable bit is dependent upon the clock edge used
for latching received data. See Figures 13—21 for placement of the
first receivable bit. The offset is the number of receive data periods
needed to align with the first bit of a time slot counting from the first
receivable bit. All subsequent receptions also follow this offset. See
Table 6 for an example of using RBOF.
CLKXI
Transmit Clock Invert.
When this bit is cleared to 0 (default), data is
transmitted on the falling edge of CLKX. If this bit is set to 1, data is
transmitted on the rising edge of CLKX.
TBOF0—TBOF2
Transmitter Bit Offset.
These 3 bits provide a fixed offset relative to
the position of the first transmittable bit position after the frame-
synchronization pulse. The position of the first transmittable bit
varies with the edge of CLKX used for data transmission. See
Figures 13—21 for placement of the first transmittable bit position.
The offset is the number of transmit data periods needed to align
with the first bit of a time slot. All subsequent transmissions also follow
this offset. See Figure 5 for an example of using TBOF.
R9
B(1—3)
R9
B4
R9
B(5—7)
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