參數(shù)資料
型號: T7121-PL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁數(shù): 56/68頁
文件大?。?/td> 685K
代理商: T7121-PL2
56
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Timing Characteristics
(continued)
(CMS = 0, CLKXI = 0, CLKRI = 1, FSPOL = 1, RBM = TBM = 11111111)
5-5049
1.Edge of clock used to sample FS (selected by the FE bit [R0—B6]).
2.Edge of first bit transmission (see Figures 12—20).
3.The CLKXI bit (R9—B4) controls the edge on which data is transmitted, and the CLKRI bit (R9—B0) controls the edge on which received data
is sampled.
Figure 23. Timing for Concentration Highway
CLKX
CLKR
TSCA
FS
(FE = 1)
DXA
AND/OR
DXB
(CLKXI = 0)
DRA
OR
DRB
(CLKRI = 1)
BIT 0
BIT 7
3
3
1
C
B
D
F
D
H
I
G
E
A
2
J
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