參數(shù)資料
型號(hào)： T7121-PL2
英文描述： T7121 HDLC Interface for ISDN
中文描述： T7121的HDLC接口用于ISDN
文件頁(yè)數(shù)： 35/68頁(yè)
文件大?。?/td> 685K
代理商： T7121-PL2
Lucent Technologies Inc.
35
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
* RLOOP and LLOOP should not be set to 1 simultaneously.
Setting RRES and TRES simultaneously returns the registers to their default values without causing the outputs to 3-state.
Table 13. Register R6—Operation Control Register
R6—B7
PDWN
(0)
R6—B6
3STATE
(0)
R6—B5
TRES
(0)
R6—B4
RRES
(0)
R6—B3
ENT
(0)
R6—B2
ENR
(0)
R6—B1
LLOOP
(0)
R6—B0
RLOOP
(0)
Register
R6
Bit
B0*
Symbol
RLOOP
Name/Function
Remote Loopback.
Setting this bit to 1 loops the received data back to
the distant end. When this bit is 0, normal transmission occurs.
Local Loopback.
Setting this bit to 1 loops transmitted data to the inter-
nal receiver. The receive data pin input (either DRA or DRB) is ignored.
Clearing this bit to 0 allows normal transmission.
Enable Receiver.
When this bit is set to 1, the received data is pro-
cessed by the receiver. When this bit is cleared to 0, incoming data is
ignored.
Enable Transmitter.
When this bit is set to 1, the transmitter is enabled,
and user data is transmitted on the selected transmit data pin(s). If no
transmit data pin is selected, the transmitter empties while the output
pins are 3-stated. When this bit is cleared to 0, the transmitter is dis-
abled. See Table 3.
Receiver Reset.
Write only. Setting this bit to 1 generates an internal
pulse that resets the HDLC receiver. The receive FIFO and related sta-
tus bits are cleared. The REOF, RF, RIDLE, and OVERRUN interrupts
are cleared. The receiver is placed in a known state.
Transmitter Reset.
Write only. Setting this bit to 1 generates an internal
pulse that resets the HDLC transmitter. The transmit FIFO's status bits
are initialized and the transmitter enters a known state. The UNDABT
interrupt is cleared and the TE interrupt is set. TDONE is cleared in
HDLC mode and set in transparent mode.
3STATE.
This bit places all HIFI-64 outputs into a high-impedance (3-
state) state. This state lasts until both
CS
and
RD
are detected low simul-
taneously.
Powerdown.
Setting this bit to 1 places the HIFI-64 into a low-power
mode. This has the effect of stopping the internal data clock and results
in significantly reduced power dissipation.
R6
B1*
LLOOP
R6
B2
ENR
R6
B3
ENT
R6
B4
RRES
R6
B5
TRES
R6
B6
3STATE
R6
B7
PDWN
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