參數(shù)資料
型號： T7121-PL2
英文描述： T7121 HDLC Interface for ISDN
中文描述： T7121的HDLC接口用于ISDN
文件頁數(shù)： 43/68頁
文件大?。?/td> 685K
代理商： T7121-PL2
Lucent Technologies Inc.
43
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
* The first occurrence of an unmasked interrupt causes the INT pin to transition. The INT pin remains active until the interrupt is acknowledged
by a read of register 15. Additional unmasked interrupts occurring before the read of register 15 do
not
cause a new transition of the INT pin,
but are reported in register 15 when it is read.
Table 24. Register R14—Interrupt Mask Register
R14—B7
TBCRC
(0)
R14—B6
RIIE
(0)
R14—B5
ROVIE
(0)
R14—B4
REOFIE
(0)
R14—B3
RFIE
(0)
R14—B2
UNDIE
(0)
R14—B1
TEIE
(0)
R14—B0
TDIE
(0)
Register
R14
Bit
B0
Symbol
TDIE
Name/Function
Transmit-Done Interrupt Enable.
When this interrupt enable bit is set, an
INT pin transition* is generated after the last bit of the closing flag or abort
sequence is sent. In the transparent mode (TRANS, AR11—B6 = 1), an INT
pin transition is generated when the transmit FIFO is completely empty.
TDIE is cleared upon reset.
Transmitter-Empty Interrupt Enable.
When this interrupt-enable bit is set,
an INT pin transition is generated when the transmit FIFO has reached the
programmed empty level (see Register 1). TEIE is cleared upon reset.
Underrun Interrupt Enable.
When this interrupt-enable bit is set, an INT
pin transition is generated when the transmit FIFO has underrun. UNDIE is
cleared upon reset. UNDIE is not used in transparent mode.
Receiver-Full Interrupt Enable.
When this interrupt-enable bit is set, an
INT pin transition is generated when the receive FIFO has reached the pro-
grammed full level (see Register 5). RFIE is cleared upon reset.
Receive End-of-Frame Interrupt Enable.
When this interrupt-enable bit is
set, an INT pin transition is generated when an end-of-frame is detected by
the HDLC receiver. REOFIE is cleared upon reset. REOFIE is not used in
transparent mode.
Receiver Overrun Interrupt Enable.
When this interrupt-enable bit is set,
an INT pin transition is generated when the receive FIFO overruns. ROVIE
is cleared upon reset.
Receiver Idle-Interrupt Enable.
When this interrupt-enable bit is set, an
INT pin transition is generated when the receiver enters the idle state. RIIE
is cleared upon reset. RIIE is not used in transparent mode.
Transmit Bad CRC.
Setting this bit to 1 forces bad CRCs to be sent on all
transmitted frames (for test purposes) until the TBCRC bit is cleared to 0.
R14
B1
TEIE
R14
B2
UNDIE
R14
B3
RFIE
R14
B4
REOFIE
R14
B5
ROVIE
R14
B6
RIIE
R14
B7
TBCRC
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