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參數(shù)資料
| 型號： | T7121-PL2 |
| 英文描述： | T7121 HDLC Interface for ISDN |
| 中文描述： | T7121的HDLC接口用于ISDN |
| 文件頁數(shù)： | 32/68頁 |
| 文件大?。?/td> | 685K |
| 代理商： | T7121-PL2 |
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32
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Note: A special block-move mode allows data to be loaded as a block to the FIFO. A block move is accomplished only in the MUXed address
and data mode by setting the BM bit in register 0 (R0—B3) to 1 and holding AD6 high during the address cycle of the ALE. All writes then
go directly to the transmit FIFO and all reads address the receive FIFO. Normal ALE mode addressing is accomplished by holding AD6
low during the ALE address cycle. Block move is enabled and disabled by the BM bit in register 0 (R0—B3).
Table 9. Register R2—Transmitter Status Register
R2—B7
TED
(1)
R2—B6
TQS6
(1)
R2—B5
TQS5
(1)
R2—B4
TQS4
(1)
R2—B3
TQS3
(1)
R2—B2
TQS2
(1)
R2—B1
TQS1
(1)
R2—B0
TQS0
(1)
Register
R2
Bit
Symbol
TQS0—TQS6
Name/Function
B(0—6)
Transmit Queue Status.
Read only. Bits 0—6 indicate how
many bytes can be added to the transmit FIFO. The bits are
encoded in binary, with bit 0 being the LSB.
Transmitter Empty Dynamic.
Read only. When this bit is
high, it indicates that the number of empty locations available
in the transmit FIFO is greater than or equal to the value pro-
grammed in the TIL bits (see register 1). This bit is cleared only
when the transmit FIFO is loaded above the preprogrammed
empty-trigger level.
R2
B7
TED
Table 10. Register R3—Data Byte Register
R3—B7
DATA7
R3—B6
DATA6
R3—B5
DATA5
R3—B4
DATA4
R3—B3
DATA3
R3—B2
DATA2
R3—B1
DATA1
R3—B0
DATA0
Register
R3
Bit
Symbol
Name/Function
B(0—7)
DATA0—DATA7
The user data bytes to be transmitted are loaded through this register
(write). Also, the user data bytes received are accessed through this
register (read).
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