XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
114
will set bit-field 2 (TxUT Parity Error Interrupt Status),
within the Transmit UTOPIA Interrupt Enable/Status
Register to “1”, as depicted below.
Once the local μP/μC has read the contents of the
Tx UT Interrupt Enable/Status register, then bit 3 of
the UNI Interrupt Status Register, Bit 2 of the TxUT
Interrupt Enable/Status register, and the INTB* output
pin will all be negated, unless outstanding interrupt
conditions are awaiting servicing.
Bit 3—TCOCA Interrupt Enable—Transmit UTOPIA
Change of Cell Alignment Interrupt Enable
This “read/write” bit-field is used for enabling or dis-
abling the “Change of Cell Alignment” interrupt. The
local microprocessor can enable this interrupt by writ-
ing a “1” to this bit-field. Upon power up or reset con-
ditions, this bit-field will contain a “0”. Therefore the
default condition is for this interrupt to be disabled.
Bit 4—TxFIFO ErrInt Enable—TxFIFO Overrun
Condition Interrupt Enable
This “Read/Write” bit-field is used for enabling or dis-
abling the “TxFIFO Overrun” interrupt. The local mi-
croprocessor can enable this interrupt by writing a “1”
to this bit. Upon power up or reset conditions, this bit
will contain a “0”. Therefore the default condition is for
this interrupt to be disabled. The local microprocessor
must write a “1” to this bit in order to enable this inter-
rupt.
Bit 5—TPerr Interrupt Enable—Detection of Parity
Error in Transmit UTOPIA Block Interrupt Enable
This “Read/Write” bit-field is used for enabling or dis-
abling the “Detected Parity error” interrupt. This inter-
rupt can be enabled by writing a “1” to this bit. Upon
power up or reset conditions, this bit will contain a “0”.
Therefore the default condition is for this interrupt to
Transmit UTOPIA Interrupt Enable /Status Register (Address-6Eh)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TxFIFO
Reset
Discard
Upon
Parity Error
TxUT Parity
Error
Interrupt
Enable
TxFIFO
Overrun
Interrupt
Enable
TCOCA
Interrupt
Enable
TxUT Parity
Error
Interrupt
Status
TxFIFO
Overrun
Interrupt
Status
TCOCA
Interrupt
Status
R/W
R/W
R/W
R/W
R/W
RUR
RUR
RUR
x
x
1
x
x
1
x
x
TxUT Interrupt Enable/Status Register (Address-6Eh)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TxFIFO
Reset
Discard
Upon Parity
Error
TxUT Parity
Error
Interrupt
Enable
TxFIFO
Overrun
Interrupt
Enable
TCOCA
Interrupt
Enable
TxUT Parity
Error
Interrupt
Status
TxFIFO
Overrun
Interrupt
Status
TCOCA
Interrupt
Status
R/W
R/W
R/W
R/W
R/W
RUR
RUR
RUR
TxUT Interrupt Enable/Status Register (Address-6Eh)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TxFIFO
Reset
Discard
Upon Parity
Error
TxUT Parity
Error
Interrupt
Enable
TxFIFO
Overrun
Interrupt
Enable
TCOCA
Interrupt
Enable
TxUT Parity
Error
Interrupt
Status
TxFIFO
Overrun
Interrupt
Status
TCOCA
Interrupt
Status
R/W
R/W
R/W
R/W
R/W
RUR
RUR
RUR