XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
PRELIMINARY
REV. P1.1.1
143
will also alert the local μP/μC of this occurrence by
generating the “Change in OOF Condition” interrupt.
To determine the framing state that the Receive
PLCP Processor is operating in, read bits 1 and 2 of
the Receive PLCP Configuration Status Register. The
bit-format of this register is presented below.
Bit 1—PLOF Status
A “1” in this bit-field indicates a “Loss of Frame” status.
Consequently, the Receive PLCP Processor will be op-
erating in the “Un-framed” state. Conversely, a “0” in
this bit-field indicates that the Receive PLCP
Processor is either in the “In-Frame” or “Out-of-
Frame” state.
Note: the state of this bit-field (and the RxLOF output pin)
is controlled by the contents of an Up/Down Counter. This
counter is incremented whenever the “POOF Status” bit is
“1” and is decremented when the “POOF Status bit is ‘0’.
However, the counter is decremented at 1/12th of the rate
that it is incremented. Therefore, when the Receive PLCP
Processor goes into the “OOF” condition, this Up/Down
Counter will increment. If the Receive PLCP Processor
requires 1ms to regain Frame-Synchronization, the PLOF
bit-field might very well be asserted, denoting an “LOF con-
dition”. However, even after the Receive PLCP Processor
has declared itself “In-Frame”, the PLOF bit-field will not be
negated until the POOF bit-field has been negated for 12 ms.
Bit 2—POOF Status
A “1” in this bit-field indicates an “Out-of-Frame”
condition. This condition necessarily indicates that
the Receive PLCP Processor is not in the “In-frame”
condition. Therefore, the user will have to read-in the
value of bit 1 in order to determine if the Receive
PLCP Processor is operating in the “Out-of-Frame” or
“Un-Framed” state.
The following table relates the “read-in” values for bits
1 and 2 to the framing state of the Receive PLCP Pro-
cessor.
4.2.2.1.4
The Receive PLCP Processor can be forced into the
“OOF” mode, via software command. This is accom-
Reframe via Software Command
plished by writing a “1” to Bit 3 in the RxPLCP Config-
uration/Status Register, as depicted below.
4.2.2.2
Once the Receive PLCP Processor enters into the “In-
frame” mode, the 12 POH bytes are then extracted and
output via a serial output port. Presently, the Receive
Overhead Byte Processing
PLCP Processor is only concerned with three (3) of
these POH bytes: B1, G1, and C1. The manner in
which the Receive PLCP Processor handles these
POH bytes follows.
RxPLCP Configuration/Status Register (Address = 44h)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Reframe
POOF Status
PLOF Status
Yellow Status
RO
RO
RO
RO
R/W
RO
RO
RO
T
ABLE
20: T
HE
R
ELATIONSHIP
BETWEEN
THE
LOGIC
STATES
OF
THE
POOF
AND
PLOF
BIT
-
FIELDS
,
AND
THE
CORRESPONDING
R
ECEIVE
PLCP F
RAMING
S
TATE
POOF B
IT
2
PLOF B
IT
1
R
ECEIVE
PLCP F
RAMING
S
TATE
0
0
In-Frame
0
1
In-Frame—PLOF is still “1” during the “12 ms period” that POOF is “0”
1
0
Out of Frame
1
1
Un-frame
RxPLCP Configuration/Status Register (Address = 44h)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Reframe
POOF Status
PLOF Status
Yellow Status
x
x
x
x
1
x
x
x