XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
38
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
Rx PLCP Processor
U25
U26
T24
T25
RxPFrame_0/
RxOHInd_0
RxPFrame_1/
RxOHInd_1
RxPFrame_2/
RxOHInd_2
RxPFrame_3/
RxOHInd_3
O
Receive PLCP Frame Indicator/Receive Overhead Indicator Output:
The exact function of this output pin depends upon whether the channel has
been configured to operate in the ATM/PLCP, the Clear-Channel Framer/Serial
or the Clear-Channel Framer/Nibble-Parallel Modes.
ATM/PLCP Mode - RxPFrame_n:
This output pin pulses "high" when the Receive PLCP Processor is receiving the
last bit of a PLCP frame.
N
OTE
:
This output pin is inactive if the XRT74L74 is configured to operate in the
Direct-Mapped ATM Mode.
Clear-Channel Framer/Serial Mode - RxOHInd_n:
This output pin pulse "high" (for one bit-period) whenever an "overhead" bit is
being output via the "RxSer_n" output pin, by the Receive Payload Data Output
Interface block.
N
OTE
:
If the user configures the channel to operate in the "Gapped-Clock"
Mode, then this output pin will provide a demand clock to the local terminal
equipment. In the "Gapped-Clock" Mode, this output pin will only provide a clock
pulse, whenever a payload bit is being output via the "RxSer_n" output pin. This
output pin will NOT generate a clock pulse, whenever an overhead is being out-
put via the "RxSer_n" output pin.
Clear-Channel Framer/Nibble-Parallel - RxOHInd_n:
This output pin pulse "high" (for one nibble-period) whenever an overhead nibble
is being output via the "RxNib_n[3:0] output pins, by the Receive Payload Data
Output Interface block.
N
OTE
:
The purpose of this output pin is to alert the local terminal equipment that
an overhead bit (or nibble) is being output via the "RxSer_n" or "RxNib_n[3:0]"
output pins and that this data should be ignored.
L24
L25
L26
L23
RxPLOF_0
RxPLOF_1
RxPLOF_2
RxPLOF_3
O
Receive PLCP - "Loss of Frame" Output Indicator:
The Receive PLCP Processor will assert this pin, when it declares a "Loss of
Frame" condition. This output will be negated when the Receive PLCP Proces-
sor reaches the "In Frame" Condition.
N
OTE
:
This output pin is only active is the XRT74L74 device has been config-
ured to operate in the ATM/PLCP Mode.
T26
T23
R24
R25
RxPOHFrame_0
RxPOHFrame_1
RxPOHFrame_2
RxPOHFrame_3
O
Receive PLCP Frame POH Serial Output Port - Frame Indicator:
This output pin, along with the "RxPOH_n" "RxPOHClk_n" and "RxPOHIns_n"
pins comprise the "Receive PLCP Frame POH Byte" serial output port. This out-
put pin provides framing information to external circuitry receiving and process-
ing this POH (Path Overhead) data, by pulsing "high" whenever the first bit of the
Z6 byte is being output via the "RxPOH_n" output pin. This pin is "low" at all
other times during this PLCP POH Framing cycle.
N
OTE
:
This output pin is only active if the XRT74L74 device has been config-
ured to operate in the ATM/PLCP Modes.
V25
V26
V23
U24
RxPOOF_0
RxPOOF_1
RxPOOF_2
RxPOOF_3
O
Receive PLCP "Out of Frame" Indicator:
The Receive PLCP Processor will assert this pin, when it declares an "Out of
Frame" condition. This output will be negated when the Receive PLCP Proces-
sor reaches the "In Frame" Condition.
N
OTE
:
This output pin is only valid if the XRT74L74 device has been configured
to operate in the ATM/PLCP Mode.