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參數(shù)資料
| 型號(hào)： | XRT86VL3x |
| 廠商： | Exar Corporation |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 52/153頁(yè) |
| 文件大?。?/td> | 1316K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
45
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
4.5
E1 Receive Overhead Interface
4.5.1
Description of the E1 Receive Overhead Output Interface Block
The E1 Receive Overhead Output Interface Block will allow an external device to be the consumer of the E1
National bit sequence. This interface provides interface signals and required interface timing to shift out proper
data link information at proper time.
The Receive Overhead Output Interface for a given Framer consists of two signals.
RxOHClk_n: The Receive Overhead Output Interface Clock Output signal
RxOH_n: The Receive Overhead Output Interface Output signal.
The Receive Overhead Output Interface Clock Output pin (RxOHCLK_n) generates a rising clock edge for
each National bit that is configured to carry Data Link information according to setting of the framer. The data
link bits extracted from the incoming E1 frames are outputted from the Receive Overhead Output Interface
Output pin (RxOH_n) before the rising edge of RxOHClk_n. The Data Link equipment should sample and latch
the data link bits at the rising edge of RxOHClk_n.
The figure below shows block diagram of the Receive Overhead Output Interface of XRT86VL3x.
4.5.2
Configure the E1 Receive Overhead Output Interface module as source of the National Bit
Sequence in E1 framing format mode
The National Bit Sequence in E1 framing format mode can be extracted and directed to:
E1 Receive Overhead Output Interface Block
E1 Receive HDLC Controller
E1 Receive Serial Output Interface
The purpose of the Receive Overhead Output Interface is to permit Data Link equipment to have direct access
to the Sa4 through Sa8 National bits that are extracted from the incoming E1 frames. Independent of the
availability of the E1 Receive HDLC Controller module, the XRT86VL3x always output the received National
bits through the Receive Overhead Output Interface block.
The XRT86VL3x allows the user to decide on the following:
How many of the National Bits is used to carry the Data Link information bits
Which of these National Bits is used to carry the Data Link information bits.
The Receive Sa Data Link Select bits of the Receive Signaling and Data Link Select Register (TSDLSR)
determine which ones of the National bits are configured as Data Link bits in E1 framing format mode.
Depending upon the configuration of the Receive Signaling and Data Link Select Register, either of the
following cases may exists:
None of the received National bits are used to transport the Data Link information bits (That is, data link
channel of XRT86VL3x is inactive).
Any combination of between 1 and all 5 of the received National bits are used to transport the Data Link
information bits.
F
IGURE
44. B
LOCK
D
IAGRAM
OF
THE
E1 R
ECEIVE
O
VERHEAD
O
UTPUT
I
NTERFACE
OF
XRT86VL3
X
Receive
Overhead Output
Interface
RxOH_n
RxOHClk_n
From Receive
Framer Block
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL3X_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3X | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
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