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參數(shù)資料
| 型號： | XRT86VL3x |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 98/153頁 |
| 文件大?。?/td> | 1316K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
91
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
The table below shows the Receive AIS State Change status bits of the Alarm and Error Status Register.
The Receive AIS State bit of the Alarm and Error Status Register (AESR), on the other hand, is a read-only bit
indicating there is AIS alarm detected in the incoming DS1 frame.
The table below shows the Receive AIS State status bits of the Alarm and Error Status Register.
9.2
Red Alarm
The Alarm indication logic within the Receive Framer block of the XRT86VL3x framer monitors the incoming
DS1 frames for red alarm or Loss of Frame (LOF) condition. Red alarm condition are detected and declared
according to the following procedure:
1.
The red alarm is detected by monitoring the occurrence of Loss of Frame (LOF) over a 6 ms interval.
2.
An LOF valid flag will be posted on the interval when one or more LOF occurred during the interval.
3.
Each interval with a valid LOF flag increments a flag counter which declares RED alarm when 63 valid
intervals have been accumulated.
4.
An interval without valid LOF flag decrements the flag counter. The Red alarm is removed when the
counter reaches zero.
If LOF condition is present in the incoming DS1 frame, the XRT86VL3x framer can generate a Receive Red
Alarm State Change interrupt associated with the setting of Receive Red Alarm State Change bit of the Alarm
and Error Status Register to one.
To enable the Receive Red Alarm State Change interrupt, the Receive Red Alarm State Change Interrupt
Enable bit of the Alarm and Error Interrupt Enable Register (AEIER) has to be set to one. In addition, the Alarm
and Error Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive Red Alarm State Change Interrupt Enable bit of the Alarm
and Error Interrupt Enable Register (AEIER).
ALARM AND ERROR STATUS REGISTER (AESR) (ADDRESS = 0XNB02H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Receive AIS State
Change
RUR /
WC
0 - There is no change of AIS state in the incoming DS1 payload data.
1 - There is change of AIS state in the incoming DS1 payload data.
ALARM AND ERROR STATUS REGISTER (AESR) (ADDRESS = 0XNB02H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
6
Receive AIS State
R
0 - There is no AIS alarm condition detected in the incoming DS1 payload
data.
1 - There is AIS alarm condition detected in the incoming DS1 payload
data.
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (ADDRESS = 0XNB03H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
2
Receive Red Alarm
State Change
Interrupt Enable
R/W
0 - The Receive Red Alarm State Change interrupt is disabled. No Receive
Red Alarm interrupt will be generated upon detection of Red Alarm condi-
tion.
1 - The Receive Red Alarm State Change interrupt is enabled. Receive
Red Alarm interrupt will be generated upon detection of Red Alarm condi-
tion.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL3X_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3X | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
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