參數(shù)資料
型號： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 60/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X
XRT86VL3X
53
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
6.0
LIU RECEIVE PATH
6.1
Line Termination (RTIP/RRING)
6.1.1
Internal Termination
The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through
RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU.
This allows one bill of materials for all modes of operation reducing the number of external components
necessary in system design. The receive termination impedance is selected by programming TERSEL[1:0] to
match the line impedance. Selecting the internal impedance is shown in
Table 5
.
The XRT86VL3x has the ability to switch the internal termination to "High" impedance by programming
RxTSEL in the appropriate channel register, if the RxTSEL hardware pin is “High”. For internal termination, set
RxTSEL to "1". By default, RxTSEL is set to "0" ("High" impedance). For redundancy applications, a
dedicated hardware pin (RxTSEL) is available to control the receive termination for all channels
simultaneously. This hardware pin is AND-ed with the register bit. Both, the register bit and the hardware pin
must be set active for the receiver to be configured for internal impedance.
Figure 55
shows a typical
connection diagram using the internal termination.
6.1.2
Equalizer Control
The main objective of the equalizer is to amplify an input attenuated signal to a pre-determined amplitude that
is acceptable to the peak detector circuit. Using feedback from the peak detector, the equalizer will gain the
input up to the maximum value specified by the equalizer control bits, in the appropriate channel register,
normalizing the signal. Once the signal has reached the pre-determined amplitude, the signal is then
processed within the peak detector and slicer circuit. A simplified block diagram of the equalizer and peak
detector is shown in
Figure 56
.
T
ABLE
5: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
TERSEL[1:0]
R
ECEIVE
T
ERMINATION
0h (00)
100
Ω
1h (01)
110
Ω
2h (10)
75
Ω
3h (11)
120
Ω
F
IGURE
55. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
R
TIP
R
RING
XRT86VL3x LIU
1:1
Internal Impedance
Line Interface T1/E1/J1
One Bill of Materials
Receiver
Input
0.1
μ
F
相關(guān)PDF資料
PDF描述
XRT86VL3X_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL3X Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT91L30_0611 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L306 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL3X_07 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VL3X_0710 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VX38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VX38_09 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VX38_0906 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
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