參數(shù)資料
型號： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 97/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X
XRT86VL3X
90
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
The Alarm Indication Signal Detection Select bits of the Alarm Generation Register (AGR) enable the two types
of AIS detection that are supported by the XRT86VL3x framer. The table below shows configurations of the
Alarm Indication Signal Detection Select bits of the Alarm Generation Register (AGR).
If detection of unframed or framed AIS alarm is enabled by the user and if AIS is present in the incoming DS1
frame, the XRT86VL3x framer can generate a Receive AIS State Change interrupt associated with the setting
of Receive AIS State Change bit of the Alarm and Error Status Register to one.
To enable the Receive AIS State Change interrupt, the Receive AIS State Change Interrupt Enable bit of the
Alarm and Error Interrupt Enable Register (AEIER) have to be set to one. In addition, the Alarm and Error
Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive AIS State Change Interrupt Enable bit of the Alarm and
Error Interrupt Enable Register (AEIER).
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
When these interrupt enable bits are set and AIS is present in the incoming DS1 frame, the XRT86VL3x framer
will declare AIS by doing the following:
Set the read-only Receive AIS State bit of the Alarm and Error Status Register (AESR) to one indicating
there is AIS alarm detected in the incoming DS1 frame.
Set the Receive AIS State Change bit of the Alarm and Error Status Register to one indicating there is a
change in state of AIS. This status indicator is valid until the Framer Interrupt Status Register is read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
ALARM GENERATION REGISTER (AGR) (ADDRESS = 0XN108H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1-0
AIS Detection
Select
R/W
00 - AIS alarm detection is disabled.When this bit is set to 01:Detection of
unframed AIS alarm of all ones pattern is enabled.
10 - AIS alarm detection is disabled.When this bit is set to 00:Detection of
framed AIS alarm of all ones pattern except for framing bits is enabled.
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (ADDRESS = 0XNB03H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Receive AIS State
Change Interrupt
Enable
R/W
0 - The Receive AIS State Change interrupt is disabled.
1 - The Receive AIS State Change interrupt is enabled.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0XNB01H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
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