參數(shù)資料
型號(hào)： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 71/153頁
文件大小： 1316K
代理商： XRT86VL3X
XRT86VL3X
64
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
X
Y
: The Xth payload bit of Channel Y
A
Y
: The signaling bit A of Channel Y
3.
After the first octet of all four channels are sent, the local Terminal Equipment start sending the second
octets following the same rules of Step 1 and 2.
The Transmit Single-frame Synchronization signal of Channel 0 pulses HIGH for one clock cycle at the first bit
position of the multiplexed data stream with data from Channel 0-3 multiplexed together. The Transmit Single-
frame Synchronization signal of Channel 4 pulses HIGH for one clock cycle at the first bit position of the data
stream with data from Channel 4-7 multiplexed together. By sampling the HIGH pulse on the Transmit Single-
frame Synchronization signal, the framer can position the beginning of the multiplexed E1 frame. It is the
responsibility of the Terminal Equipment to align the multiplexed transmit serial data with the Transmit Single-
frame Synchronization pulse.
Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are
de-multiplexed inside the XRT86VL3x device and send to each individual channel. These data will be
processed by each individual framer and send to LIU interface. The local Terminal Equipment provides a free-
running 2.048MHz clock to the Transmit Serial Input clock of each channel. The framer will use this clock to
carry the processed payload and signaling data to the transmit section of the device.
Figure 69
shows how to
connect the Transmit multiplexed high-speed Input Interface block to local Terminal Equipment.
Figure
shows
the timing signals when framer is running at 16.384MHz Bit-Multiplexed mode.
HMVIP/ H100 16.384Mbit/s Byte-Multiplexed Mode
When the Transmit Multiplex Enable bit is set to one and the Transmit Interface Mode Select [1:0] bits are set
to 10, the Transmit Back-plane interface of framer is running at HMVIP 16.384MHz. When Transmit Interface
Mode Select[1:0] bits are set to 11, the Transmit Back-plane interface is running at H100 16.384MHz mode.
The Transmit Back-plane Interface is accepting data through TxSer_0 or TxSer_4 pins at 16.384Mbit/s. The
local Terminal Equipment multiplexes payload data of every four channels into one data stream. Payload data
of Channel 0-3 are multiplexed onto the Transmit Serial Data pin of Channel 0. Payload data of Channel 4-7
are multiplexed onto the Transmit Serial Data pin of Channel 4.
Free-running clocks of 16.384MHz is supplied to the Transmit Input Clock pin of Channel 0 and Channel 4 of
the framer. The local Terminal Equipment provides multiplexed payload data at rising edge of this Transmit
Input Clock. The Transmit High-speed Back-plane Interface of the framer then latches incoming serial data at
falling edge of the clock.
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
6
0
B
0
6
1
B
1
6
2
B
2
6
3
B
3
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
7
0
C
0
7
1
C
1
7
2
C
2
7
3
C
3
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
8
0
D
0
8
1
D
1
8
2
D
2
8
3
D
3
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