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參數(shù)資料
| 型號(hào)： | XRT86VL3x |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 53/153頁(yè) |
| 文件大?。?/td> | 1316K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
46
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
The table below shows configuration of the Receive Sa Data Link Select bits of the Receive Signaling and Data
Link Select Register (RSDLSR).
For every received Sa bit that is determined to carry Data Link information, the Receive Overhead Output
Interface will supply a clock pulse, via the RxOHClk_n output pin, such that:
The Receive Overhead Output interface should update the data on the RxOH_n line before the rising edge of
RxOHClk_n.
The external Data Link equipment interfaced to the Receive Overhead Output Interface will sample and latch
the data on the RxOH_n line on the rising edge of RxOHClk_n.
Figure 45
below shows the timing diagram of the output signals associated with the E1 Receive Overhead
Output Interface module in E1 framing format mode.
RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (ADDRESS = 0XN10CH)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
7
Receive Sa8 Data
Link Select
R/W
0 - The received Sa8 Nation bit is not extracted to the data link interface.
1 - The received Sa8 Nation bit is extracted to the data link interface.
6
Receive Sa7 Data
Link Select
R/W
0 - The received Sa7 Nation bit is not extracted to the data link interface.
1 - The received Sa7 Nation bit is extracted to the data link interface.
5
Receive Sa6 Data
Link Select
R/W
0 - The received Sa6 Nation bit is not extracted to the data link interface.
1 - The received Sa6 Nation bit is extracted to the data link interface.
4
Receive Sa5 Data
Link Select
R/W
0 - The received Sa5 Nation bit is not extracted to the data link interface.
1 - The received Sa5 Nation bit is extracted to the data link interface.
3
Receive Sa4 Data
Link Select
R/W
0 - The received Sa4 Nation bit is not extracted to the data link interface.
1 - The received Sa4 Nation bit is extracted to the data link interface.
F
IGURE
45. E1 R
ECEIVE
O
VERHEAD
O
UTPUT
I
NTERFACE
T
IMING
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL3X_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3X | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
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