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| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計中的應(yīng)用說明 |
| 文件頁數(shù)： | 12/52頁 |
| 文件大小： | 687K |
| 代理商： | 21329 |
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2
Processor Models and Steppings
AMD-K6
Processor BIOS Design
21329L/0—December 1999
Processor Models and Steppings
There are four models within the AMD-K6 family of
processors—Models 6, 7, 8, and 9:
Model 6 (AMD-K6 processor Model 6)
—This processor is
manufactured in the 0.35-micron process. The Model 6
supports six Model-Specific Registers (MSRs).
Model 7
(AMD-K6 processor Model 7)
—This is the first
processor manufactured in the 0.25-micron process. The
Model 7 implements the same six MSRs as the Model 6, and the
bits and fields within these six MSRs are defined identically.
Model 8
(AMD-K6-2 processor Model 8)
—This processor is
also manufactured in the 0.25-micron process. Some
important features supported by the Model 8 include the
3DNow! instruction set and support for a 100-MHz
processor bus. This document covers the following two
specific stepping ranges of the Model 8:
Model 8/[7:0]
is any of eight possible model/steppings—
Models 8/0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, or 8/7. Model 8/[7:0]
implements the same six MSRs as the Models 6 and 7,
and the bits and fields within these six MSRs are defined
identically.
Model
8/[7:0]
SYSCALL/SYSRET Target Address Register (STAR)
MSR for a total of seven MSRs.
Model 8/[F:8]
is any of eight possible model/steppings—
Models 8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, or 8/F. Model
8/[F:8] implements the same six MSRs as the Models 6, 7,
and 8/[7:0], but the bits and fields within two of these
MSRs are not defined identically. Also, Model 8/[F:8]
supports the STAR MSR and three additional MSRs, for a
total of ten MSRs.
Model 9
(
AMD-K6-III processor Model 9
)—This processor is
also manufactured in the 0.25-micron process. In addition to
supporting the 3DNow! instruction set and a 100-MHz
processor bus, the Model 9 contains a 256-Kbyte backside L2
cache. The Model 9 implements the same six MSRs as the
Models 6, 7, and 8/[7:0], but the bits and fields within two of
these MSRs are not defined identically. Also, the Model 9
supports the STAR MSR and four additional MSRs, for a
total of eleven MSRs.
I
I
I
also
implements
the
I
Table 6 on page 14 summarizes the MSR differences between
the models and steppings of the AMD-K6 family of processors.
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