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| 型號(hào)： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明 |
| 文件頁數(shù)： | 36/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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26
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
means of “Write to a Cacheable Page” or “Write to a Sector.” It
is not safe to perform write allocations between 640 Kbytes and
1 Mbyte (000A_0000h to 000F_FFFFh) because it is considered
a noncacheable region of memory. Additionally, if a memory
region is defined as write-combinable or uncacheable by a
MTRR, write allocates are not performed in that region.
SYSCALL/SYSRET
Target Address
Register (STAR)
The STAR register in the AMD-K6-2 processor Model 8/[F:8] is
identical to the implementation of this register in the Model
8/[7:0]. See “SYSCALL/SYSRET Target Address Register
(STAR)” on page 19.
UC/WC Cacheability
Control Register
(UWCCR)
The AMD-K6-2 processor Model 8/[F:8] provides two variable-
range Memory Type Range Registers (MTRRs)—MTRR0 and
MTRR1—that each specify a range of memory. Each range can
be defined as one of the following memory types:
I
Uncacheable (UC) memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address and a
write allocation does not occur.
Write-Combining (WC) memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
Note:
The MTRRs defined in this document are not software
compatible to the MTRRs defined by the Pentium Pro and
Pentium II processors.
I
The programmer accesses the MTRRs by addressing the 64-bit
MSR known as the UC/WC Cacheability Control Register
(UWCCR). The MSR address of the UWCCR is C000_0085h.
Following reset, all bits in the UWCCR register are set to 0.
MTRR0 (lower 32 bits of the UWCCR register) defines the size
and memory type of range 0 and MTRR1 (upper 32 bits) defines
the size and memory type of range 1 (see Figure 7).
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