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參數(shù)資料
| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計中的應(yīng)用說明 |
| 文件頁數(shù)： | 33/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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Model-Specific Registers (MSRs)
23
21329L/0—December 1999
AMD-K6
Processor BIOS Design
I
If GEWBED equals 0 and SEWBED equals 0, the processor
enforces strong ordering for all internal and external write
cycles. In this setting, the processor assumes, or
speculates
,
that strong order must be maintained between writes to the
merge buffer and writes that hit the processor’s cache. Once
the merge buffer is written out to the processor’s bus, the
EWBE# signal is sampled. If EWBE# is sampled negated, the
processor delays the commitment of write cycles to
processor cache lines in the modified state or exclusive state
until EWBE# is sampled asserted.
This setting is the default after RESET and provides the
lowest performance of the three settings because full write
ordering is maintained.
Table 10 summarizes the three settings of the EWBEC field for
the EFER register, along with the effect of write ordering and
performance.
Enforcing complete write ordering in a uniprocessor system is
usually not necessary. In order to achieve the highest level of
performance while still maintaining support for the EWBE#
signal, AMD recommends that the BIOS set EFER[3:2] to 01b
(close-to-best performance). Many uniprocessor systems do not
support the EWBE# signal, in which case AMD recommends
that the BIOS set EFER[3:2] to 10b or 11b (best performance).
Write Handling
Control Register
(WHCR)
The AMD-K6-2 processor Model 8/[F:8] contains a split level-1
(L1) 64-Kbyte writeback cache organized as a separate
32-Kbyte instruction cache and a 32-Kbyte data cache with
two-way set associativity. The cache line size is 32 bytes, and
lines are read from memory using an efficient pipelined burst
read cycle. Further performance gains are achieved by the
implementation of a write allocation scheme.
Table 10. EWBEC Settings
EFER[3]
(GEWBED)
EFER[2]
(SEWBED)
Write
Ordering
Performance
1
0 or 1
None
Best
0
1
All except UC/WC
Close-to-Best
0
0
All
Slowest
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