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| 型號(hào)： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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22
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
cache. In general, the ordering of write cycles that are driven
externally on the system bus and those that hit the processor’s
cache can be controlled by the EWBE# signal. If EWBE# is
sampled negated, the processor delays the commitment of write
cycles to cache lines in the modified state or exclusive state in
the processor’s cache. Therefore, the system logic can enforce
strong ordering by negating EWBE# until the external write
cycle is complete, thereby ensuring that a subsequent write
cycle that hits the cache does not complete ahead of the
external write cycle.
However, the addition of the write merge buffer introduces the
potential for out-of-order write cycles to occur between writes
to the merge buffer and writes to the processor’s cache. Because
these writes occur entirely within the processor and are not
sent out to the processor bus, the system logic is not able to
enforce strong ordering with the EWBE# signal.
The EWBE control (EWBEC) bits provide a mechanism for
enforcing three different levels of write ordering in the
presence of the write merge buffer:
I
EFER[3] is defined as the Global EWBE Disable
(GEWBED). When GEWBED equals 1, the processor does
not attempt to enforce any write ordering internally or
externally (the EWBE# signal is ignored). This is the
maximum performance setting.
EFER[2] is defined as the Speculative EWBE Disable
(SEWBED). SEWBED only affects the processor when
GEWBED equals 0. If GEWBED equals 0 and SEWBED
equals 1, the processor enforces strong ordering for all
internal write cycles with the exception of write cycles
addressed to a range of memory defined as uncacheable
(UC) or write-combining (WC) by the MTRRs. In addition,
the processor samples the EWBE# signal. If EWBE# is
sampled negated, the processor delays the commitment of
write cycles to processor cache lines in the modified state or
exclusive state until EWBE# is sampled asserted.
This setting provides performance comparable to, but
slightly less than, the performance obtained when
GEWBED equals 1 because some degree of write ordering is
maintained.
I
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