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參數(shù)資料
| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計中的應(yīng)用說明 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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Model-Specific Registers (MSRs)
17
21329L/0—December 1999
AMD-K6
Processor BIOS Design
Note:
The AMD-K6 processor Models 6 and 7 provide the SCE bit
in the EFER register, but this bit does not affect processor
operation because the SYSCALL and SYSRET instructions
and the STAR register are not supported in these models.
Write Handling
Control Register
(WHCR)
The processor contains a split level-1 (L1) 64-Kbyte writeback
cache organized as a separate 32-Kbyte instruction cache and a
32-Kbyte data cache with two-way set associativity. The cache
line size is 32 bytes and lines are read from memory using an
efficient pipelined burst read cycle. Further performance gains
are achieved by the implementation of a write allocation
scheme.
A write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 cache. For more information
on write allocate, see the
Implementation of Write Allocate in the
K86 Processors Application Note
, order# 21326, and the Cache
Organization section of the
AMD-K6
Processor Data Sheet
,
order# 20695 or the
AMD-K6
-2
Processor Data Sheet
, order#
21850.
This section describes two programmable mechanisms used by
the processor to determine when to perform write allocate.
When either of these mechanisms indicates that a pending
write is to a cacheable area of memory, a write allocate is
performed.
Before enabling write allocate or changing memory
cacheability/writeability, the BIOS must writeback and
invalidate the internal cache by using the WBINVD instruction.
In addition, write allocate should be enabled only after
performing any memory sizing or typing algorithms.
The Write Handling Control Register (WHCR) is a MSR that
contains three fields—the WCDE bit, the Write Allocate
Enable Limit (WAELIM) field, and the Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit (see Figure 3).
Table 7.
Extended Feature Enable Register (EFER) Definition (Models 6, 7, and 8/[7:0])
Bit
Description
R/W
Function
63–1
Reserved
R
Writing a 1 to any reserved bit causes a general protection
fault to occur. All reserved bits are always read as 0.
SCE must be set to 1 to enable the usage of the SYSCALL and
SYSRET instructions.
0
System Call Extension (SCE)
R/W
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