參數(shù)資料
型號(hào): 21329
英文描述: AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note
中文描述: 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說(shuō)明
文件頁(yè)數(shù): 42/52頁(yè)
文件大?。?/td> 687K
代理商: 21329
32
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
LINPAGE.
This 20-bit field must be written with bits 31:12 of the
linear address of the 4-Kbyte page that is to be invalidated and
optionally flushed from the L1 cache.
PF.
If an attempt to invalidate or flush a page results in a page
fault, the processor sets the PF bit to 1, and the invalidate or
flush operation is not performed (even though invalidate
operations do not normally generate page faults). In this case,
an actual page fault exception is not generated. If the PF bit
equals 0 after an invalidate or flush operation, then the
operation executed successfully. The PF bit must be read after
every write to the PFIR register to determine if the invalidate
or flush operation executed successfully.
F/I.
This bit is used to control the type of action that occurs to
the specified linear page. If a 0 is written to this bit, the
operation is a flush, in which case all cache lines in the
modified state within the specified page are written back to
memory, after which the entire page is invalidated. If a 1 is
written to this bit, the operation is an invalidation, in which
case the entire page is invalidated without the occurrence of
any writebacks.
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