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| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明 |
| 文件頁數(shù)： | 49/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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Model-Specific Registers (MSRs)
39
21329L/0—December 1999
AMD-K6
Processor BIOS Design
Figure 15. L2 Data - EAX
If the L2 tag is read (as opposed to reading the cache data), the
result is placed in EAX in the format as illustrated in Figure 16.
Similarly, if the L2 tag is written, the write data is taken from
EAX.
When writing to the L2 tag, special consideration must be given
to the least significant bit of the Tag field of the EAX register—
EAX[15]. The length of the L2 tag required to support the
256-Kbyte L2 cache on the Model 9 is 16 bits, which corresponds
to bits 31:16 of the EAX register. However, the processor
provides a total of 17 bits for storing the L2 tag—that is, 16 bits
for the tag (EAX[31:16]), plus an additional bit for internal
purposes (EAX[15]). During normal operation, the processor
ensures that this additional bit (bit 15) always corresponds to
the set in which the tag resides. Note that bits 15:6 of the
address determine the set, in which case bit 15 equal to 0
addresses sets 0 through 511, and bit 15 equal to 1 addresses
sets 512 through 1023.
In order to set the full 17-bit L2 tag properly when using the
L2AAR register, EAX[15] must likewise correspond to the set in
which the tag is being written—that is, EAX[15] must be equal
to EDX[15] (refer to Figure 14 and Figure 16).
It is important to note that this special consideration is only
required if the processor will subsequently be expected to
properly execute instructions or access data from the L2 cache
following the setup of the L2 cache by means of the L2AAR
register. If the intent of using the L2AAR register is solely to
test or debug the L2 cache without the subsequent intent of
executing instructions or accessing data from the L2 cache,
then this consideration is not required.
When accessing the L2 tag, the Line, Octet, and Dword fields of
the EDX register are ignored.
0
31
Data
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