參數(shù)資料
型號(hào)： 21329
英文描述： AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note
中文描述： 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說(shuō)明
文件頁(yè)數(shù)： 46/52頁(yè)
文件大?。?/td> 687K
代理商： 21329
36
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
STEP.
This read-only field contains the stepping ID. This is
identical to the value returned by CPUID standard function 1 in
EAX[3:0].
BF.
This read-only field contains the value of the BF signals
sampled by the processor during the falling transition of
RESET, which allows the BIOS to determine the frequency of
the host bus. The core frequency must first be determined using
the Time Stamp Counter method (See “Time Stamp Counter
(TSC)” on page 15). The core frequency is then divided by the
processor-clock to bus-clock ratio as determined by the BF field
of the PSOR register (see Table 13 on page 31). The result is the
frequency of the processor bus.
Page Flush/Invalidate
Register (PFIR)
The PFIR register in the AMD-K6-III processor Model 9 is
identical to the implementation of this register in the Model
8/[F:8]. See “Page Flush/Invalidate Register (PFIR)” on
page 31. The invalidate and flush operations affect the
processor’s L1 and L2 caches on the Model 9.
Level-2 Cache Array
Access Register
(L2AAR)
The AMD-K6-III processor Model 9 provides the L2AAR
register that allows for direct access to the L2 cache and L2 tag
arrays. The 256-Kbyte L2 cache in the AMD-K6-III processor is
organized as shown in Figure 12:
I
Four 64-Kbyte ways
Each way contains 1024 sets
Each set contains four 64-byte sectors (one sector in each
way)
Each sector contains two 32-byte cache lines
Each cache line contains four 8-byte octets
Each octet contains an upper and lower dword (4 bytes)
I
I
I
I
I
Each line within a sector contains its own MESI state bits, and
associated with each sector is a tag and LRU (Least Recently
Used) information.
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