參數(shù)資料
型號(hào): 21329
英文描述: AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note
中文描述: 的AMD - K6處理器電源設(shè)計(jì)應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用說明
文件頁數(shù): 51/52頁
文件大?。?/td> 687K
代理商: 21329
New AMD-K6
Processor Instructions
41
21329L/0—December 1999
AMD-K6
Processor BIOS Design
New AMD-K6
Processor Instructions
All models of the AMD-K6 processor implement the following
new instruction set:
I
MMX Instructions—57 new instructions for multimedia
software. See the
AMD-K6
Processor Multimedia Technology
Manual
, order# 20726 for more information.
AMD-K6-2 processor Models 8 and above, and the AMD-K6-III
processor Model 9 implement the following new instructions:
I
3DNow! Instructions—21 new instructions for multimedia
software. See the
3DNow! Technology Manual
, order#
21928 for more information.
SYSCALL and SYSRET—See the
SYSCALL and SYSRET
Instruction Specification Application Note
, order# 21086 for
more information.
I
Additional Considerations
Software Timing
Dependencies
Relative to Memory
Controller Setup
Processors in the K86 family differ from other processors with
regards to instruction latencies and the order or priority of
processor bus cycles. Timing-dependent software that relies on
the specific latencies of other processors should be re-tested for
proper operation with the K86 processor. In addition, re-testing
should be performed on components with variable timing (such
as, memory modules, oscillators, and timers).
Particular attention should be paid to memory-setup
subroutines that determine the type of DRAM in the system.
Some chipsets may not tolerate a DRAM mode change (such as,
EDO to SDRAM) on the same clock as a DRAM refresh cycle.
For example some chipsets do not tolerate having its memory
refresh enabled prior to changing memory mode types. Refresh
should only be enabled after the memory type has been
determined.
Note:
The BIOS for the K86 family of processors should enable the
write allocate mechanisms only after performing any
memory sizing or typing algorithms.
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