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參數(shù)資料
| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設計應用指南的AMD - K6處理器的BIOS設計中的應用說明 |
| 文件頁數(shù)： | 34/52頁 |
| 文件大小： | 687K |
| 代理商： | 21329 |
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24
Model-Specific Registers (MSRs)
AMD-K6
Processor BIOS Design
21329L/0—December 1999
A write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 cache. For more information
on write allocate, see the
Implementation of Write Allocate in the
K86 Processors Application Note
, order# 21326 and the Cache
Organization section of the
AMD-K6
-2
Processor Data Sheet
,
order# 21850 or the
AMD-K6
-III Processor Data Sheet
, order#
21918.
This section describes two programmable mechanisms used by
the AMD-K6-2 processor Model 8/[F:8] to determine when to
perform write allocate. When either of these mechanisms
indicates that a pending write is to a cacheable area of memory,
a write allocate is performed.
Before enabling write allocate or changing memory
cacheability, the BIOS must write back and invalidate the
internal cache by using the WBINVD instruction. In addition,
write allocate should be enabled only after performing any
memory sizing or typing algorithms.
The Write Handling Control Register (WHCR) is a MSR that
contains two f
ields—the Write Allocate Enable Limit
(WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte
(WAE15M) bit (see Figure 6).
Note:
The WHCR register as defined in the Model 6, Model 7, and
Model 8/[7:0] has changed in the Model 8/[F:8].
Figure 6. Write Handling Control Register (WHCR)—MSR C000_0082h (Model 8/[F:8])
15
22
0
63
Reserved
WAELIM
16
W
A
E
1
5
M
Note
:
Hardware RESET initializes this MSR to all zeros.
Symbol
WAELIM
WAE15M
Description
Write Allocate Enable Limit
Write Allocate Enable 15-to-16-Mbyte 16
Bits
31-22
17
21
31
32
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