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參數(shù)資料
| 型號： | 21329 |
| 英文描述： | AMD-K6 Processor Power Supply Design Application Note AMD-K6 Processor Bios Design Application Note |
| 中文描述： | 的AMD - K6處理器電源設(shè)計應(yīng)用指南的AMD - K6處理器的BIOS設(shè)計中的應(yīng)用說明 |
| 文件頁數(shù)： | 45/52頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 21329 |
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Model-Specific Registers (MSRs)
35
21329L/0—December 1999
AMD-K6
Processor BIOS Design
using an efficient pipelined burst read cycle. In addition, the
AMD-K6-III processor also contains a 256-Kbyte, 4-way set
associative, unified level-2 (L2) cache. Further performance
gains are achieved by the implementation of a write allocation
scheme.
The WHCR register in the AMD-K6-III processor Model 9 is
identical to the implementation of this register in the Model
8/[F:8].
See “Write Handling Control Register (WHCR)” on
page 23.
Note:
The WHCR register as defined in the Model 6, Model 7, and
Model 8/[7:0] has changed in the Model 9.
SYSCALL/SYSRET
Target Address
Register (STAR)
The STAR register in the AMD-K6-III processor Model 9 is
identical to the implementation of this register in the Model
8/[7:0]. See “SYSCALL/SYSRET Target Address Register
(STAR)” on page 19.
UC/WC Cacheability
Control Register
(UWCCR)
The UWCCR register in the AMD-K6-III processor Model 9 is
identical to the implementation of this register in the Model
8/[F:8]. See “UC/WC Cacheability Control Register (UWCCR)”
on page 26.
Processor State
Observability
Register (PSOR)
The AMD-K6-III processor Model 9 provides the Processor State
Observability Register (PSOR) (see Figure 11).
.
Figure 11.
Processor State Observability Register (PSOR
)—MSR C000_0087h (Model 9)
NOL2.
This read-only bit indicates whether the processor
contains an L2 cache. This bit is always set to 0 for Model 9.
2
0
63
BF
Reserved
Description
No L2 Functionality
Processor Stepping
Bus Frequency Divisor
Symbol
NOL2
STEP
BF
Bit
8
7-4
2-0
3
4
STEP
7
8
9
N
O
L
2
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