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參數(shù)資料
| 型號(hào)： | 30046-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術(shù)處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁(yè)數(shù)： | 151/247頁(yè) |
| 文件大?。?/td> | 4379K |
| 代理商： | 30046-23 |
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Revision 1.2
151
www.national.com
Integrated Functions (
Continued
)
G
GX_BASE+833Ch-833Fh
C_FP_H_TIMING Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
26:16
RSVD
Reserved:
Set to 0.
Flat Panel Horizontal Sync End:
The pixel count at which the flat panel horizontal sync signal
becomes inactive minus 1.
Reserved:
Set to 0.
Flat Panel Horizontal Sync Start:
The pixel count at which the flat panel horizontal sync signal
becomes active minus 1.
Note:
These values are specified in pixels rather than character clocks to allow precise control over sync position. For flat panels
which combine two pixels per panel clock, these values should be odd numbers (even pixel boundary) to guarantee that the
sync signal will meet proper setup and hold times.
FP_H_SYNC
_END
RSVD
FP_H_SYNC
_START
15:11
10:0
GX_BASE+8340h-8343h
DC_V_TIMING_1 Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
26:16
RSVD
V_TOTAL
Reserved:
Set to 0.
Vertical Total:
The total number of lines for a given frame scan minus 1. The value is necessarily
greater than the V_ACTIVE field because it includes border lines and blanked lines. If the display is
interlaced, the total number of lines must be odd, so this value should be an even number.
Reserved:
Set to 0.
Vertical Active:
The total number of lines for the displayed portion of a frame scan minus 1. For flat
panels, if this value is less than the panel active vertical resolution (V_PANEL), the parameters
V_BLANK_START, V_BLANK_END, V_SYNC_START, and V_SYNC_END should be reduced by
the following value (V_ADJUST) to achieve vertical centering: V_ADJUST = (V_PANEL
–
V_ACTIVE) / 2
If the display is interlaced, the number of active lines should be even, so this value should be an odd
number.
Note:
These values are specified in lines.
15:11
10:0
RSVD
V_ACTIVE
GX_BASE+8344h-8347h
DC_V_TIMING_2 Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
26:16
RSVD
Reserved:
Set to 0.
Vertical Blank End:
The line at which the vertical blanking signal becomes inactive minus 1. If the
display is interlaced, no border is supported, so this value should be identical to V_TOTAL.
Reserved:
Set to 0.
Vertical Blank Start:
The line at which the vertical blanking signal becomes active minus 1. If the
display is interlaced, this value should be programmed to V_ACTIVE plus 1.
Note:
These values are specified in lines. For interlaced display, no border is supported, so blank timing is implied by the total/active
timing.
V_BLANK_END
15:11
10:0
RSVD
V_BLANK_
START
GX_BASE+8348h-834Bh
DC_V_TIMING_3 Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
26:16
15:11
10:0
RSVD
Reserved:
Set to 0.
Vertical Sync End:
The line at which the CRT vertical sync signal becomes inactive minus 1.
Reserved:
Set to 0.
Vertical Sync Start:
The line at which the CRT vertical sync signal becomes active minus 1. For
interlaced display, note that the vertical counter is incremented twice during each line and since
there are an odd number of lines, the vertical sync pulse will trigger in the middle of a line for one
field and at the end of a line for the subsequent field.
Note:
These values are specified in lines.
V_SYNC_END
RSVD
V_SYNC_START
GX_BASE+834Ch-834Fh
DC_FP_V_TIMING Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:27
26:16
RSVD
Reserved:
Set to 0.
Flat Panel Vertical Sync End:
The line at which the flat panel vertical sync signal becomes inactive
minus 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal sync
prior to being output to the panel.
Reserved:
Set to 0.
Flat Panel Vertical Sync Start:
The line at which the internal flat panel vertical sync signal
becomes active minus 2. Note that the internal flat panel vertical sync is latched by the flat panel
horizontal sync prior to being output to the panel.
Note:
These values are specified in lines.
FP_V_SYNC
_END
15:11
10:0
RSVD
FP_VSYNC
_START
Table 4-31. Display Controller Timing Registers (Continued)
Bit
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 300471U | Radial, -55dotc, long life wsitching-power |
| 300CNQ | SCHOTTKY RECTIFIER |
| 300CNQ035 | SCHOTTKY RECTIFIER |
| 300CNQ040 | SCHOTTKY RECTIFIER |
| 300CNQ045 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 30046-46L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 73MM |
| 300-466A | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9325 |
| 300-466B | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9324 |
| 300-466K | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9322 |
| 300-466R | 制造商:LG Corporation 功能描述:FRONT CABINET |
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