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218
Revision 1.2
Instruction Set (
Continued
)
G
CALL
Subroutine Call
Direct Within Segment
Register/Memory Indirect Within Segment
Direct Intersegment
-Call Gate to Same Privilege
-Call Gate to Different Privilege No Par
’
s
-Call Gate to Different Privilege m Par
’
s
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
Indirect Intersegment
-Call Gate to Same Privilege
-Call Gate to Different Privilege No Par
’
s
-Call Gate to Different Privilege m Par
’
s
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
CBW
Convert Byte to Word
CDQ
Convert Doubleword to Quadword
CLC
Clear Carry Flag
CLD
Clear Direction Flag
CLI
Clear Interrupt Flag
CLTS
Clear Task Switched Flag
CMC
Complement the Carry Flag
CMOVA/CMOVNBE
Move if Above/Not Below or Equal
Register, Register/Memory
CMOVBE/CMOVNA
Move if Below or Equal/Not Above
Register, Register/Memory
CMOVAE/CMOVNB/CMOVNC
Move if Above or Equal/Not Below/Not Carry
Register, Register/Memory
CMOVB/CMOVC/CMOVNAE
Move if Below/Carry/Not Above or Equal
Register, Register/Memory
CMOVE/CMOVZ
Move if Equal/Zero
Register, Register/Memory
CMOVNE/CMOVNZ
Move if Not Equal/Not Zero
Register, Register/Memory
CMOVG/CMOVNLE
Move if Greater/Not Less or Equal
Register, Register/Memory
CMOVLE/CMOVNG
Move if Less or Equal/Not Greater
Register, Register/Memory
CMOVL/CMOVNGE
Move if Less/Not Greater or Equal
Register, Register/Memory
CMOVGE/CMOVNL
Move if Greater or Equal/Not Less
Register, Register/Memory
CMOVO
Move if Overflow
Register, Register/Memory
CMOVNO
Move if No Overflow
Register, Register/Memory
CMOVP/CMOVPE
Move if Parity/Parity Even
Register, Register/Memory
CMOVNP/CMOVPO
Move if Not Parity/Parity Odd
Register, Register/Memory
E8 +++
FF [mod 010 r/m]
9A [unsigned full offset,
selector]
-
-
-
-
-
-
-
-
-
3
3
b
h,j,k,r
3/4
9
3/4
14
24
45
51+2m
183
189
123
186
192
126
15
25
46
52+2m
184
190
124
187
193
127
3
2
1
4
6
7
3
FF [mod 011 r/m]
11
98
99
F8
FC
FA
0F 06
F5
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
x
3
2
1
4
6
7
3
m
l
c
0F 47 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 46 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 43 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 42 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 44 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 45 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 4F [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 4E [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 4C [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 4D [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 40 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 41 [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 4A [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
0F 4B [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
r
Table 7-27. Processor Core Instruction Set Summary (Continued)
Instruction
Opcode
Flags
Real
Mode
Prot’d
Mode
Real
Mode
Prot’d
Mode
O D I
F
F
T
F
S Z
F
A P C
F
F
F
F
F
Clock Count
(Reg/Cache Hit)
Issues